Other Parts Discussed in Thread: HALCOGEN
Hi,
I want to test "Primary SRAM Hard Error Cache and Livelock " mechanism.
Following is my understanding about this mechanism:
(1) If there is ECC livelock fault, ESM Group2 channel16 will be set.
(2) As long as ESM 2.16 was set, the processor will go into "FIQ void esmHighInterrupt(void)". "FIQ void esmHighInterrupt(void)" is generate by HALCoGen v 04.06.01.
Q1: Does my understanding right?
I found some example code in in Safe TI Diagnostic Library v 2.3.1.
case SRAM_LIVELOCK_DIAGNOSTICS:
(void)SL_FLAG_SET(testType);
tp = (volatile uint64 *)0x08000004u; /*start address of unaligned access*/
eccB1 = (volatile uint64 *)0x08000000u; /*bank1 base word*/
/*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
eccB1 = eccB1 + (0x00400000u/sizeof(uint64)); /*pointer to ecc for bank1 base word*/
eccB2 = (volatile uint64 *)0x08000008u; /*bank2 base word*/
/*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
eccB2 = eccB2 + (0x00400000u/sizeof(uint64)); /*pointer to ecc for bank2 base word*/
/* Enable Writes to ECC RAM */
/*SAFETYMCUSW 9 S MR: 12.2 <APPROVED> Comment_10*/
/*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> Comment_5*/
BIT_SET(tcram1REG->RAMCTRL, TCRAM_RAMCTRL_ECCWREN);
/*SAFETYMCUSW 9 S MR: 12.2 <APPROVED> Comment_10*/
/*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> Comment_5*/
BIT_SET(tcram2REG->RAMCTRL, TCRAM_RAMCTRL_ECCWREN);
regBkupRamTh1 = tcram1REG->RAMTHRESHOLD;
regBkupRamTh2 = tcram2REG->RAMTHRESHOLD;
/* set threshold to 1 */
tcram1REG->RAMTHRESHOLD = 0x1u;
tcram2REG->RAMTHRESHOLD = 0x1u;
_SL_Barrier_Data_Access();
/* cause a 1-bit ECC error */
*eccB1 ^= TCRAM_SYN_1BIT_DATA_ECC;
*eccB2 ^= TCRAM_SYN_1BIT_DATA_ECC;
/* read from location with to be generate error */
_SL_Barrier_Data_Access();
ramread64 = (*tp); /*unaligned read*/
_SL_Barrier_Data_Access();
SL_FLAG_CLEAR(testType);
break;
However , when I test the above code in debug mode step by step, I can only see there generate 1-bit ECC Error but ESM 2.16 is not set.
Q2: Does anything wrong?
