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TMS570 Interrupt priorities

Richard Burke
Expert 1910 points


It is my understanding that the TMS570 effectively has only two interrupt priorities, IRQ and FIQ. Whilst the CHANMAP mechanism provides a way to rank interrupts in priority order, this only applies when two interrupts are pending and an IRQ interrupt cannot be interrupted by a higher priority IRQ interrupt.

Could you please confirm that my understanding is correct? Are there any techniques that can be used to enable higher priority interrupts to interrupt lower priority interrupts (other than the FIQ mechanism)?

Thanks,

Richard

  • 0
    TI__Prodigy 365 points

    Hi Richard,

    Q1 :- It is my understanding that the TMS570 effectively has only two interrupt priorities,

    Ans :- Yes, the TMS570 has 2 interrupts, Normal Interrupt request (IRQ) and Fast Interrupt Request (FIQ). And the FIQ has higher priority compared to the IRQ.

    Q2 :- Whilst the CHANMAP mechanism provides a way to rank interrupts in priority order.

    Ans :- Yes the Channel mapping provides a way to control the priority of the interrupt channels. The interrupt control register (CHANCTRL x) is a 32 bit register where in each byte determines the mapping of interrupt requests to the interrupt channels. The interface between the interrupt control register and priority channels [CHANxx] is one to one i.e.  CHANCTRL0 register controls channel mapping 0, 1, 2, 3; CHANCTRL1 register controls channel mapping 4, 5, 6, 7; and so on.

    Therefore configuring CHANMAPx0 [6:0]. Bits in Interrupt Control register 0 [CHANCTRL0] determines which interrupt request is mapped to the priority channel CHANx0.

    Note :- The lowest channel has the higher priority. For example Channel0 has higher priority than Channel1; similarly Channel 63 has a higher priority over Channel 64.

    Q3:- this only applies when two interrupts are pending and an IRQ interrupt cannot be interrupted by a higher priority IRQ interrupt.

    Ans :- Yes, when an IRQ interrupt occurs it disables all the further IRQ interrupts by setting the 'I' bit in the CPSR (current program status register). once the current IRQ interrupt is serviced it enables the IRQ interrupts by clearing the 'I' bit in CPSR and then the highest pending IRQ is serviced.

    Q4 :- Are there any techniques that can be used to enable higher priority interrupts to interrupt lower priority interrupts (other than the FIQ mechanism)?

    Ans :-  Yes Nesting of interrupts is possible if an only u enable the IRQ interrupts by clearing the 'I' bit (in CPSR) in the current ISR, then the highest pending IRQ is serviced.


    Regards

    Hari


  • 0 in reply to Hari49672
    TI__Mastermind 22375 points

    Richard,

     

    I would like to add some comments on your question.

    The TMS570LS series supports 2 types of interrupts. IRQ and FIQ. The FIQ (Fast Interrupt) are treated has NMI, meaning that the CPU cannot mask them by setting the F bit in the CPSR.This is an option available on the Cortex R4F to treat FIQ as NMI. (This hardware configuration cannot be changed)
    Out of reset, both IRQ and FIQ/NMI are disable. Once the F bit is cleared in the CPSR, FIQ/NMI are enable and the F bit cannot be set again.

    The VIM Req0 (ESM) and Req 1(reserved) are mapped to channel 0 and Channel 1 on the VIM. These request cannot been masked, cannot been re-mapped to another channel and are always treated as NMI (FIQ) (See note on page 1726 of SPNU489)
    .
    In other words, if a request is present on VIM Req0 or Req 1 the CPU will always enter the NMI(FIQ) exception.

    By default,  the CPU does not support nested IRQ. The I bit in CPSR is automatically set to disable any other IRQ request.
    Anyway, it is possible to support nested Interrupt by software by re-enabling IRQ (clearing the I bit in CPSR).
    Your IRQ interrupt handler will have to take care of all context saving, including general purpose registers, Link Register....

    Regards,

    Jean-Marc

  • 0 in reply to Jean-Marc Mifsud
    Intellectual 715 points

    Hello Jean,

    If I use FIQ instead of IRQ mapping for VIM Channels other than 0 and 1, then will I be able to disable [MASK off] those channels using the F-Bit of CPSR?

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan
    Expert 1910 points

    Hi Pashan,

    Once FIQ interrupts have been enabled, they cannot be disabled via the CPSR register (see section 24.2.1 at the top of page 1744 in the Technical Reference Manual). As the manual states, the FIQ implemented in Cortex-R4F is Non-Maskable Fast Interrupts (NMFI).

    Regards,

    Richard

  • 0 in reply to Richard Burke
    Intellectual 715 points

    Hello Richard,

    Is the above reply of yours related to F-Bit of CPSR also valid for TMS470PSF764 parts?

    I mean FIQ will not be disabled at the CPU Core using F-Bit of CPSR Register.

    I am assuming ARM7TDMI CPU Core is being used inside TMS470PSF764 devices.

    Please confirm.

    Thank you.

    Regards

    Pashan

  • 0 in reply to Pashan
    Expert 1910 points

    Hi Pashan,

    I'm sorry but I can't answer your question about the TMS470. I only know about the TMS570 having wrestled with the VIM and interrupts over the last few weeks. You might be better posting the question to the TMS470 forum.

    Regards,

    Richard 

  • 0 in reply to Pashan
    TI__Prodigy 365 points

    Hi Pashan,

    I have forwarded your query to our expert team, will get back to asap.

    Regards

    Hari

  • 0 in reply to Pashan
    TI__Mastermind 22375 points

    Pashan,

     

    The TMS470PSF64 is an ARM7 based microcontroller.
    On this device, there is no concept of NMI. Interrupt can be IRQ or FIQ.

    The I and F bit in the CPSR are used to enable and disable IRQ and FIQ on the CPU side.

    On the VIM, channel 0 and 1 are always configured as FIQ. All other channels can be set as IRQ or FIQ.

     

     

    Best Regards,

    Jean-Marc

  • 0 in reply to Jean-Marc Mifsud
    Expert 1315 points

    (TMS570LC43, CCS55, FreeRtos)

    I'm trying to configure two interrupts in IRQ, one from my highest priority interrupt from VIM_HET1_HIGH channel (0x0A) and the other from VIM_RTI_COMPARE_0 channel (0x02). (The last one is my RTOS interrupt).

    My goal is to have nesting on both, but VIM_HET1_HIGH shall have higher priority than the VIM_RTI_COMPARE_0.

    So I guess I have to configure VIM priority. Is it possible to reverse both priority ?

    My normal VIM config is:

    regVim.chanCtl.all[0] = 0x00010203UL;

    regVim.chanCtl.all[1] = 0x04050607UL;

    regVim.chanCtl.all[2] = 0x08090A0BUL;

    regVim.chanCtl.all[3] = 0x0C0D0E0FUL;

    ...

    So I've tried many ways in order to reverse the order of both, like for instance:

    regVim.chanCtl.all[0] = 0x00010A03UL; //02 to 0A

    regVim.chanCtl.all[1] = 0x04050607UL;

    regVim.chanCtl.all[2] = 0x0809020BUL; //0A to 02

    regVim.chanCtl.all[3] = 0x0C0D0E0FUL;

    One or another interrupt never come at all.

     

    Note:

    One way to prioritize NHET is to put it in FIQ, but the performance is low and this interrupt is high frequency. Could you confirm that FIQ have lowest performance than IRQ ?

     

    Simon

     

     

  • 0 in reply to Simon lapointe
    TI__Guru**** 191906 points

    Hi Simon,

      At the first glance I don't see a problem with your code reassigning the channels between NHET and RTI. After you swap the channels, did you also update the VIM RAM for the corresponding ISR addresses for these two interrupts? They need to be swapped as well.

      In the VIM INTREG0 register did you see both NHET and RTI flags set?

      If you disable one of the interrupts will you see the other one generating?

      The FIQ is higher priority than IRQ from the CPU architecture point of view. The FIQ is a fast interrupt request. If the CPU receives both the IRQ and FIQ at the same time it will service FIQ first.

      

  • 0 in reply to Charles Tsai
    Expert 1315 points

    Yes it helps, both interrupts are generated now after swaping the channels. After a while, my NHET interrupt ceases though, I have to investiguate, it could be application related. I've got about 9 hits on NHET, after that it ceases.
    Another question: if I want nesting interrupt (only preampt the RTOS interrupt, not the opposite), I guess I have to clear interrupt flag within the ISR of the RTOS, on the RTI ?

  • 0 in reply to Simon lapointe
    TI__Guru**** 191906 points
    First of all, when an IRQ is received, the ARM processor will disable further interrupts by setting the 'I' bit in the CPSR register. You can clear the 'I' bit in the ISR to allow nested interrupts.