TMS570LS3137: TMS570 bus interfaces and DAP connection

Hello Fabio,

The interconnect is provided in the block diagrams in the datasheet and TRM. The DAP is connected through SCR1 AHB and can access the CPU, SRAM, FLASH, Other Masters, and peripherals in the device.

Detail view from the datasheet:

Architectural Block diagram from the technical reference manual:

Hi, Chuck. Thanks for your answer.

I have seen these images before. But it is not clear to me.

1)  As shown in first figure, DAP has two outputs: 

             a. One connected to AHB interface via AHB matrix (Figure 2). Does the core have an AHB slave port?

             b. One connected to APB interface. Where is this in Figure 2?

2) What does "A2A" (Figure 1) mean?

Regards,

Fabio

Hello Fabio:

It may be helpful to review the CoreSight Architecture Specification from the ARM infocenter at this link:

Fabio Nazzi said:

a. One connected to AHB interface via AHB matrix (Figure 2). Does the core have an AHB slave port?

No. The DAP has access to all Masters in the system (the only registers the DAP cannot access are the PMM registers).

Fabio Nazzi said:

     b. One connected to APB interface. Where is this in Figure 2?

This is a highlevel view. In reality, the bus interfaces are built into the SCRS noted in the block diagram. Note that the AHB and APB are just the protocols to "speak" to the various components on the VBUSM/BMM bus,

Fabio Nazzi said:

2) What does "A2A" (Figure 1) mean?

A2A = AHB to APB interface. Its a bus to bus translator/bridge.

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