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RM48L952: HALCoGen: ADC ADEVSAMP-register value restrictions

Jarkko Silvasti
Expert 1395 points
Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

Hello,

TRM clearly says that:
SW = EV ACQ + 2 in terms of ADCLK cycles.

And requires that:
First, the ADC module design  requires that SW >= 3 ADCLK cycles.

This would mean that EV ACQ cannot be ever 0, but HALCoGen still happily puts 0 to that register without issuing any warnings?

Is the TRM correct and why value 0 is even possible to put that register in case it is always illegal value?

  • 0
    TI__Guru 59540 points
    Hello Jarkko,

    The requirement listed in the TRM is accurate as a minimum. Also, you need to be aware of the requirements as stated in the Datasheet relative to minimum sample times. The value in this field where SW>=3 ADCLK cycles will need to be adjusted to accommodate the minimum sample time dependent on your configured ADCLK settings. For example, the minimum sample/hold time as stated in the datasheet is 0.2us and the minimum ADCLK cycle is 0.033 (30MHz). IF this is the case, then the minimum cycles for the sample time would be 0.2/0.033 = 6.1 or 7 moving to the next slowest time based on the resolution of the bits.

    For the former issue of a minimum of at least 3, I will enter a HalCoGen CQ ticket to address this issue. For the latter issue, it is a configuration dependent limitation, so this is up to the system integrator to understand the limitations as set forth in the Datasheet.