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RM48L952: SafeTI: ADC self test

Part Number: RM48L952
Other Parts Discussed in Thread: LM20

Hello,

1) what is the meaning of ADC_PIN_UNDETERMINED, is the test failed or not?

2) SafeTI user manual requires that sampling time must be exactly 1us, is this correct?
NOTE: The application must ensure that the sampling time of ADC event group is set to 1us before calling this API

3)  Does Cext affect to self test so that sampling time should be set according to it. What would be correct sampling time in case Cext is a) 200nF b) 100nF?

4) Why self test looks to work in case I put ADCLK as slow as possible (prescale 31) -> 290,91ns cycle time and then select 1us as sample time which results to 1,163us actual sample time (tTotal is in this case 9,993us) but does not work (returns undetermined) in case ADCLK is set to 100ns (prescale 10) and sample time is 1us as required in safeTI user manual (tTotal is 4,64us in this case)? It does not help if sample time is increased say to 1,5us. (tTotal 5,64us) or to 4us (tTotal 10,64us) where in 4us case the total time is longer than with slower ADCLK case which looks to work

5) Why this test looks to occasionally pass and in next  debugger reset it may fail. We have 2 channels which both has temperature sensors connected and 200nF case fails much often than other but both fails in case ADC CLK is 100ns and looks to work with slowest possible ADCLK. Basically you will need to some time easily run the test at least 5 times to get that error....

Actual reading of the sensors looks to work dispite of the settings, both sensors gives consistent readings which are also inside tolerance compared to other sensors so actual ADC functionality looks to work, the problem is only that SafeTI testing.

Selftest is passed reading like this is received (ADCLK prescale 31 == 290,91ns) - this looks to work always

Vu 1494
Vn 1489
Vd 1486
refhi 4095
reflo 0

And in case of failure ADCLK 100ns the Vn == Vu but range of values stays pretty much same
Vu 1511
Vn 1511
Vd 1510
refhi 4095
reflo 0

With 100ns ADCLK and 200ns sample time (which violates EV ACQ, should be 300ns?) the refHI rises only to 3957 but still these case may sometimes success with circuit which has 100nF (and also with that 200nF circiut in case the capasitor is changed to 100nF), in that case Vn is always Vu-1 and Vd is Vn-2.

There was some other threads like this but that didn't gave 100% understanding are we doing something wrong or not? Obviously somewhere are problem but where and would there be problems in multiple areas like requiring 1us time in manual and in out sampling config...
https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/356661?tisearch=e2e-quicksearch&keymatch=ADC%20self%20test

Circuit 1 (300R resistor and 100nF capasitor):
vREf---meas_chip---300R------------ADPIN23
                                                  || 100nF
                                               GND

Circuit 2 (10K resistor and 200nF capasitor):
vREF---10K-------------------ADPIN0
                       |             || 200nF
                10k NTC   GND
                  GND

  • Hello Jarkko,

    I wasn't able to get to you question today, but it will be addressed before the end of the work.
  • Hello Jarko,

    1. The ADC pin status is defined as: good, open, shorted to High, shorted to low, and undetermined

    2. The calibration conversion needs to meet the minimum sampling time specification for the ADC. This value is typically 1 us. (TRM)

    3. The sample time for the ADC is defined by the ADCLK frequency and the AD<GROUP>SAMP register for each conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel. If the sample time is insufficient, then the charge left on the sample capacitor by the previous conversion of a channel can affect the accuracy of the channel currently being converted. This phenomenon is referred to as channel-to-channel crosstalk. To add a capacitor onto ADC pin will lower the source impedance of the channel, and the internal sample capacitor will be charged quickly. The RC (Rsource and Cext) time constant should be less than a value which is related to  the group cycle time or tTotal(time from start of sampling to the start of next sampling).

    4/5: Can you enable the discharge of the sampling capacitor and try again? This feature is to discharge Csamp between conversions. The minimum time required to perform this discharging process is typically about 1 to 2 ADC clock cycles. 

    Regards,

    QJ

  • Hi,

    1. I know the possible return values, the question was "if undetermined is returned, is the test failed or not", I assume that it is failed but that is not said anywhere, the circuits itself are 100% ok so this is not a HW problem in terms of short circuit or anything like it?

    2. Data sheet in table 7-9 says that minimum time is 200ns (td(SH)). From power up it is 1us (td(PU-ADV) but it is not said clearly in TRM which time is meant, since minimum & sampling is mentioned I assume that it means 200ns. In any case the SafeTI user manual requires "exactly" 1us - that is wrong it should be "equal or greater than X" what ever the X is...

    3. What is Rsource? In the link in first post there is Rext and Cext outside the CPU, Rext==Rsource? Our RC is 10k*200nF == 2ms and 300R*100nF == 30us (this is what LM20 ~suggests). Does it really mean that we would need to set sampling time to greater than 2ms since NTC-circuit has such RC? Why selftest then works if tTotal is ~10us when just ADCLK is set to as slow as possible? Our normal continuous conversion cycle is 10ms which should be ok (as a cycle time) since we measure only these 2 channels.

    4/5. Added discharge (3 ADCLK) - does not help. Maybe lowered a probability for undetermined result a bit (this is not exact science;)),
        adcREG1->EVSAMPDISEN = (uint32)((uint32)3U << 8U)
                             | (uint32)0x00000001U;

    Adding discharge changed a latter meas (LM20 in channel 23) result in continuous cycle a bit (temperature dropped from 38C to 36C (is this a indication that currently we have some cross-talk in the system?). Adding discharge to 100 ADCLK does not change behavior further the temperature stays in 36C. We have also very accurate (+-0,5C) SPI-bus based sensor on board and it shows 38C so I think that 38C from LM20 is more correct than 36C (both of these sensors (SPI&LM20) are quite close to each other distance about 1cm and both are located on same side & edge of the board so temperature should be quite similar).

    Then I set ADCLK as slow as possible and set sampling time as long as possible. That resulted to 2411us total time where sampling time is ~1,2ms (discharge 10us used)... Selftest works (but it works also if tTotal is ~10us in case ADCLK is as slow as possible). Now the measured LM temperature rised again back to 38degree and we also got that same value as we got originally with 100ns ADCLK and 3,42us tTotal  (300ns sampling time) without discharge (this was our "original config"). So looks like that sampling time does not have meaningful effect.

    In case our external RC's are 2ms and 30us (as presented in first posts "ascii circuit"), you should be able to tell us correct AD config to use so that it matches to every restriction of the CPU?

    For me this looks like that 100ns cycle in "real use" with rather short sampling time (3,4us) looks to work as well as any other config, self test requires (in order to NOT return 'undetermined') slowest possible ADCLK (tTotal does not matter so sampling time could be quite fast). This combination sounds crazy...
    - Based on the link in first post (and picture in it) I understood that Rext is meaningless in selftest phase...

    I have also set NOPs and tested with debugger than loop is gone through. It does not matter to self test result whether the 1us loop is on place or not.
            adcInit();
            uint32 u32Wait = (uint32)HCLK_FREQ; // in Mhz, converts straight to us
            while( u32Wait-- )
            {
                __asm( "nop" );
            }
    It looks like based on TRM that this 1us wait is only needed when ADC module is put to power down mode manually and wake up after that. Currently I made these selftest tests as suggested phase in web-link after every other SafeTI tests (so the adc module should have had power more than 1us after startup so that NOP-loop after init is meaningless) http://www.ti.com/lit/an/spna106d/spna106d.pdf 

    I changed that 200nF to 100nF (so RC is 1ms) and with same "as long as possible what can be configured" sample time 1,2ms the calculated ADC results is as far away from measured actual value with oscillosscope as with much shorter sample time... Now sample time should exceed RC but it does not change anything (discharge 4xADCLK this time)...

    Also it should be noticed that even completely wrong config where ADEVSAMP is set to 0 (EV ACQ must be at least 1 on order to meet required 3 in TRM) the results are still similar as if register value is 1...

    Tried to also consult our HW guy who designed the measuring circuits but he couldn't say anything even after re-reading TRM & e2e topics concerning ADC. We can change Cext in NTC circuit smaller if that helps but based on my experiment the biggest problem is still the self test random undetermined result, everything else works or at least looks to be working (good enough to not see obvious errors) even our config could be completely wrong and/or RC is out of range what we can measure with 110 VCLK...

    I have tried by trial & guessing tens of different configs but as usually, trial&guessing seldom gives the correct results so I gave up and made the thread so please give exact ADC timing config for given RC's. In TRM 19-13 the Cext looks to be discharged "completely" during selftest, that cannot be the purpose/meaning of the test since it won't happen in our case...

  • I am taking words back about discharge and its effects, it does not look to have any effect (that 2 degree change had to be related to the fact that CPU was idling before I made the change). Bit of tricky to say anything for sure since ADC inputs are constantly changing based on temperature but I am 99,9% sure about this...

    Now LM looks to show ~same temperature despite of discharge setting so basically same results are received despite of sample time or tTotal or ADCLK (tried 100ns and 291ns).

    So only self test requires ADCLK to be slowest possible (~291ns) does not work reliably with 100ns ADCLK even if EVSAMP is 4095. Incase ADCLK is 291ns it does not matter is EVSAMP 1 (~800ns sample) or 2 (~1us) sample) both looks to give consistent PIN_GOOD results.
  • Hi Jarkko,

    1) ADC_PIN_UNDETERMINED, how I interpret this is that pin connection to silicon is OK, as Vu != refhi and Vd != reflo. Also the connection is not shorted to refhi or reflo as in that case all measurements should be about the same to one where shorted and this is not the case. For getting good results test is expecting that Vd < Vn < Vu. In your case Vu == Vn and thus test returns UNDETERMINED. Why you are getting same result is either that pin is shorted to some voltage between refhi and reflo, or what seems to be in your case because of ADC external circuitry. As in Vu measurement, refhi is muxed internally in Hercules to ADC pin and in Vd measurement reflo. Of course there are some resistance internally at IC on these connections and the bigger driving capability your external circuitry has to ADC pin, the smaller variation you have on these measurements. Also Cext has effect to the measurements, as the bigger your Cext is longer it takes it to charge/discharge to stable value. You can see the principle of self-test described in TRM chapter 19.8.2 and in picture below (from this chapter) you can see R1 and R2.

    Unfortunately values of these seems not to be specified in documentation, at https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/356661 you can see picture with values of 5K and 7K, but we'll need to double check and confirm if these are the values. Also in ADC there are internal resistances on sampling and muxing, max values of Rsamp and Rmux are specified in datasheet, in any case I believe those are significantly smaller than R1 & R2. Also in datasheet internal capacitance values for sampling and muxing is specified.
    I know this is not as explicit answer as you may have wished for, I think you should internally discuss with your HW designer and system architect if you want to change your external circuitry so that you should not get this UNDETERMINED result, and use ADCLK so that ensures the pin voltage has time to stabilize or to decide if this situation is OK for you.

    3) Like described above, AD pin external circuitry has effect to self-test. This is because for the Vu and Vd measurement refhi and reflo are connected to pin correspondingly. Thus in these cases ADC internal and external components will form the whole circuitry and thus also external components define the voltage value on these measurement and also the time it takes the voltage to to be charged/discharged to this value.

      -Jani