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TMS570LC4357: Difference between LS and LC architecture.

Szilard Lovas
Expert 1425 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: TPS65381-Q1, , TMS570LS1224, HALCOGEN

Hi,

I've just realized the meaning of LC as I started to read tps65381-q1.pdf.
Could you guys recommend some more reading on LC (loosely-coupled) architecture?
Regards, Szilárd

  • 0
    TI__Guru**** 197036 points
    Hi Szilard,

    LS means Lockstep, and LC stands for Lockstep with Cache.

    Regards,
    QJ
  • 0 in reply to QJ Wang
    Expert 1425 points

    Hi QJ,
    Thank you for the prompt answer.

    Regarding to tps65381-q1.pdf section 1.3:

    "The TPS65381-Q1 device is a multi-rail power supply designed to supply microcontrollers (MCUs) in functional safety applications,
    such as those found in automotive and industrial applications. The device supports Texas Instruments ’ TMS570LS series flash MCU and
    other MCUs with dual-core lockstep (LS) or loosely-coupled architectures (LC)"

    So its a bit specious. Could you give me an example for loosely-coupled architecture Texas MCU?

    Is it kind an SMP (symmetric multi processing - two independent core with common memory) ?

    Regards, Szilárd

  • 0 in reply to Szilard Lovas
    TI__Guru**** 197036 points
    Hello Szilard,

    It might mean the dual-core processors which have the shared the memory and cache.

    Regards,
    QJ
  • 0 in reply to Szilard Lovas
    TI__Mastermind 20590 points

    Hi Szilard,

    I support the TPS65381(A)-Q1.   The comment about loosely coupled is after the phrase "and other MCUs with...".  The TPS65381(A)-Q1 is a companion chip with tight support for the TMS570/Hercules which have dual core lock step to meet a chip set approach to the safety architecture. However not all functional safety applications use lock step.  The TPS65381(A)-Q1 also supports many other MCUs, some from TI such as the C2000, TMS470, and other MCU vendors.  Some of those have a loosely-coupled dual core approach, which may require additional software and hardware for example to reach certain safety goals.  A generic definition of loosely-coupled can be found on Wikipedia: https://en.wikipedia.org/wiki/Loose_coupling

    So yes, it is generically it could independent cores either with common memory or separate memories. 

    Best Regards,

    Scott

  • 0 in reply to Scott Monroe
    Expert 1425 points

    Hi Scott,

    Thank you very much for the details. I just can't get it out of my mind that TMS570LC4357 meant to be a real
    dual core (split lock) MCU.

    Regards, Szilárd

  • 0 in reply to Szilard Lovas
    Expert 1226 points
    In addition to the above post by QJ Wang, there is also another thread specifying that the LC in TMS570LC4357 stands for "lockstep cache", as opposed to the LS == "lockstep (and tightly coupled memory" that most of other TMS570 parts have:

    e2e.ti.com/.../1254554

    What I can't tell myself, is what the safety implications are.

    In the LC design, does each CPU of the dual lock-stepped CPUs have its own independent cache, or is there only a single shared cache?

    Assuming that we have ECC enabled in all cases, are there any failure scenarios we need to analyze if we move from a cache-less LS design (such as the TMS570LS1224) to a cached LC design (specifically the TMS570LC4357)?

    --thx
  • 0 in reply to 1138
    TI__Mastermind 20590 points
    Please use the other post from the MCU team on what LC and LS means to the TMS570.

    The original response to the PMIC datasheet says " It might mean the dual-core processors which have the shared the memory and cache.", however this response was not from the PMIC team or any one who wrote LS or LC in the TPS65381(A)-Q1 datasheet.

    As I wrote in my original response for TPS65381(A)-Q1 datasheet viewpoint LS = lock-step dual core and LC = loosely-coupled dual core.

    These short acronyms (LS and LC) may not be used in the same way by the TMS570 team. As I mentioned the TPS65381(A)-Q1 is a companion chip to many different MCUs, FPGAs and DSPs, not just TMS570. We try to keep it as broad of a power supply as possible.

    Best Regards,
    Scott
  • 0 in reply to Scott Monroe
    Expert 1425 points

    Hi,
    Could you Guys tell me, where the "Lockstep mode" signal comes from? (spnu563, page: 489)

    Regards, Szilárd

  • 0 in reply to Szilard Lovas
    Expert 1425 points

    Just one more question..

    does the following note means that in the self-test mode both CPU can drive the bus independently? (spnu563, page: 491)

    Regards: Szilárd

  • 0 in reply to Szilard Lovas
    Expert 1425 points

    I have made a simple led blinking demo for trying to decouple the cores with the self-test mode in the CCM-R5 module.
    I don't know if it was successful or not, because the blinking speed was the same. I think it could be same because the two
    cores has only 2 clock difference and the first two stages of the 8 stage pipeline are prefetch stages.

    So (I think) an additional single core reset should be needed.

    I started to digging into TRM and found this:

    Its nothing interesting, but the HALCoGen generated code was a bit more talkative..

    Maybe somebody has an idea, how to reset a single core for testing..

    8037.SplitLockTest.zip

    Regards, Szilárd

  • 0 in reply to Szilard Lovas
    Guru 92251 points

    Szilard Lovas said:
    I just can't get it out of my mind that TMS570LC4357 meant to be a real dual core (split lock) MCU.

    The Split/lock section of the Cortex-R5 Technical Reference Manual says:

    The Cortex-R5 processor can be configured so that it can be switched, under reset, between a twin-CPU performance mode and a dual-redundant safety mode. This feature imposes extra constraints on the software usage model. Contact ARM for information on how it can be used.

    I am not sure if the ability to select "twin-CPU performance mode" is an option available in all devices, or if it a feature the device manufacturer has to enable as an option in the macrocell.

  • 0 in reply to Chester Gillon
    Expert 1425 points

    Hi Chester,
    Thank you for your comment!
    I have read the mentioned TRM. It is visible that the split lock signals are not connected to any pins outside.
    The real question that is it possible to decouple the CPU cores and get CPU2 to drive the BUS.

    Yesterday I could reset CPU2 independently by STC module. Unfortunately I couldn't experience any
    signs of CPU2 BUS interaction in spite of switching CCM module to self-test mode which actually should separate the cores.

    Regards, Szilárd

  • 0 in reply to 1138
    TI__Guru 59540 points

    Hello 1138,

    There is only one Cache memory not lock stepped memory. The Cache is also protected by ECC, but it is not automatically enabled and must be enabled by the application SW. As far as the device architecture is considered, there were/are additional mechanisms that had to be accounted for and which have been added to the device's safety manual and FMEDA tool. Certainly, you cannot simply port some code from an LS device to the LC without some major overhaul since there is an updated CPU as well as an updated architecture to support the cache architecture and different Master/slave interactions. In the LC device the memory is not tightly coupled since RAM and Flash reside on the L2 bus instead of the TCMs.

    There may be other safety points that should be considered at the system level.

  • 0 in reply to Szilard Lovas
    TI__Guru 59540 points
    Hello Szilard,

    The cores cannot be decoupled. There was initially some discussion to allowing this mode of operation (thus the input signal to indicate lockstep mode), but the unlocked version never made it to production and was canceled. As you have seen, there may be some remnants of this left in the documentation but the device is dedicated to only lockstep operation. Any attempts to use it otherwise are not supported or recommended.
  • 0 in reply to Chuck Davenport
    Expert 1425 points

    Hi Chuck,
    Thank you for the explanation. I think we are more close to the original meaning of "LC".
    I always loved the etymology :)

    Regards, Szilárd