CCS/TM4C129ENCPDT: Problem with dma configuration for using both ADC

Sergio Mamani

Tool/software: Code Composer Studio

I do not know why while using this code the program gets stuck in the IntDefaultHandler(void) in the start up file, i know that is because an unexpected interruption was called, what I want to know is what is wrong with this code:

void ADCconfigure(uint32_t sysclock)

{
    SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_ADC0);
    ADCClockConfigSet(ADC0_BASE,ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_FULL, 1);          //Clock source (Precision Internal Clock)

    ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_TIMER, 0);  // SS0-SS3 priorities must always be different
    ADCSequenceStepConfigure(ADC0_BASE, 1, 0, ADC_CTL_CH0);
    ADCSequenceStepConfigure(ADC0_BASE, 1, 1, ADC_CTL_CH1);
    ADCSequenceStepConfigure(ADC0_BASE, 1, 2, ADC_CTL_CH2);
    ADCSequenceStepConfigure(ADC0_BASE, 1, 3, ADC_CTL_CH3 | ADC_CTL_END | ADC_CTL_IE);
    ADCSequenceDMAEnable(ADC0_BASE, 1);

    uDMAChannelAttributeDisable(UDMA_CHANNEL_ADC1,
                                    UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST |
                                    UDMA_ATTR_HIGH_PRIORITY |
                                    UDMA_ATTR_REQMASK);

    uDMAChannelControlSet(UDMA_CHANNEL_ADC1 | UDMA_PRI_SELECT,
                            UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
                              UDMA_ARB_1);

    uDMAChannelControlSet(UDMA_CHANNEL_ADC1 | UDMA_ALT_SELECT,
                            UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
                              UDMA_ARB_1);
    /**/
    uDMAChannelTransferSet(UDMA_CHANNEL_ADC1 | UDMA_PRI_SELECT,
                               UDMA_MODE_PINGPONG,
                               (void *)(ADC0_BASE + ADC_O_SSFIFO1),
                               g_ui8RxBufA[0], MEM_BUFFER_SIZE);

    uDMAChannelTransferSet(UDMA_CHANNEL_ADC1 | UDMA_ALT_SELECT,
                                UDMA_MODE_PINGPONG,
                                (void *)(ADC0_BASE + ADC_O_SSFIFO1),
                                g_ui8RxBufB[0], MEM_BUFFER_SIZE);

    uDMAChannelEnable(UDMA_CHANNEL_ADC1);
    ADCIntEnableEx(ADC0_BASE, ADC_INT_DMA_SS1);
    IntEnable(INT_ADC0SS1);

    SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
    SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_ADC1);
    ADCClockConfigSet(ADC1_BASE,ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_FULL, 1);

    ADCSequenceConfigure(ADC1_BASE, 1, ADC_TRIGGER_TIMER, 1);
    ADCSequenceStepConfigure(ADC1_BASE, 1, 0, ADC_CTL_CH16);
    ADCSequenceStepConfigure(ADC1_BASE, 1, 1, ADC_CTL_CH17);
    ADCSequenceStepConfigure(ADC1_BASE, 1, 2, ADC_CTL_CH18);
    ADCSequenceStepConfigure(ADC1_BASE, 1, 3, ADC_CTL_CH19 | ADC_CTL_END | ADC_CTL_IE);   // ADC_CTL_IE fires every 8 samples
    ADCPhaseDelaySet(ADC1_BASE, ADC_PHASE_0);
    ADCSequenceDMAEnable(ADC1_BASE, 1);

    uDMAChannelAttributeDisable(UDMA_CH25_ADC1_1,
                                    UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST |
                                    UDMA_ATTR_HIGH_PRIORITY |
                                    UDMA_ATTR_REQMASK);

    uDMAChannelControlSet(UDMA_CH25_ADC1_1 | UDMA_PRI_SELECT,
                            UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
                              UDMA_ARB_8);

    uDMAChannelControlSet(UDMA_CH25_ADC1_1 | UDMA_ALT_SELECT,
                            UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
                              UDMA_ARB_8);

    uDMAChannelTransferSet(UDMA_CH25_ADC1_1 | UDMA_PRI_SELECT,
                               UDMA_MODE_PINGPONG,
                               (void *)(ADC1_BASE + ADC_O_SSFIFO1),
                               g_ui8RxBufA[1], MEM_BUFFER_SIZE);

    uDMAChannelTransferSet(UDMA_CH25_ADC1_1 | UDMA_ALT_SELECT,
                                UDMA_MODE_PINGPONG,
                                (void *)(ADC1_BASE + ADC_O_SSFIFO1),
                                g_ui8RxBufB[1], MEM_BUFFER_SIZE);

    uDMAChannelAssign(UDMA_CH25_ADC1_1);
    uDMAChannelEnable(UDMA_CH25_ADC1_1);
    ADCIntEnableEx(ADC1_BASE, ADC_INT_DMA_SS1);
    IntEnable(INT_ADC1SS1);
//--------------------------------------------------------------------
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
    TimerConfigure(TIMER0_BASE, TIMER_CFG_A_PERIODIC);
    TimerLoadSet(TIMER0_BASE, TIMER_A, sysclock/(125000)/*(48000*8*2)*/);
    TimerControlTrigger(TIMER0_BASE, TIMER_A, true);
    TimerEnable(TIMER0_BASE, TIMER_A);
    ADCSequenceEnable(ADC0_BASE, 1);
    ADCSequenceEnable(ADC1_BASE, 1);
}

After using the IntEnable(INT_ADC0SS1); the problem appears, I was using before this code, that use Seq 0 and everything works well:

void ADCconfigure(uint32_t sysclock)

{
    SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_ADC0);
    ADCClockConfigSet(ADC0_BASE,ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_FULL, 1);          //Clock source (Precision Internal Clock)

    ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_TIMER, 0);  // SS0-SS3 priorities must always be different
    ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_CH0);         // PE3
    ADCSequenceStepConfigure(ADC0_BASE, 0, 1, ADC_CTL_CH1);         // PE2
    ADCSequenceStepConfigure(ADC0_BASE, 0, 2, ADC_CTL_CH2);         // PE1
    ADCSequenceStepConfigure(ADC0_BASE, 0, 3, ADC_CTL_CH3);         // PE0
    ADCSequenceStepConfigure(ADC0_BASE, 0, 4, ADC_CTL_CH0);
    ADCSequenceStepConfigure(ADC0_BASE, 0, 5, ADC_CTL_CH1);
    ADCSequenceStepConfigure(ADC0_BASE, 0, 6, ADC_CTL_CH2);
    ADCSequenceStepConfigure(ADC0_BASE, 0, 7, ADC_CTL_CH3 | ADC_CTL_END | ADC_CTL_IE);
    ADCSequenceDMAEnable(ADC0_BASE, 0);

    uDMAChannelAttributeDisable(UDMA_CHANNEL_ADC0,
                                    UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST |
                                    UDMA_ATTR_HIGH_PRIORITY |
                                    UDMA_ATTR_REQMASK);

    uDMAChannelControlSet(UDMA_CHANNEL_ADC0 | UDMA_PRI_SELECT,
                            UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
                              UDMA_ARB_1);

    uDMAChannelControlSet(UDMA_CHANNEL_ADC0 | UDMA_ALT_SELECT,
                            UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
                              UDMA_ARB_1);
    /**/
    uDMAChannelTransferSet(UDMA_CHANNEL_ADC0 | UDMA_PRI_SELECT,
                               UDMA_MODE_PINGPONG,
                               (void *)(ADC0_BASE + ADC_O_SSFIFO0),
                               g_ui8RxBufA[0], MEM_BUFFER_SIZE);

    uDMAChannelTransferSet(UDMA_CHANNEL_ADC0 | UDMA_ALT_SELECT,
                                UDMA_MODE_PINGPONG,
                                (void *)(ADC0_BASE + ADC_O_SSFIFO0),
                                g_ui8RxBufB[0], MEM_BUFFER_SIZE);

    uDMAChannelEnable(UDMA_CHANNEL_ADC0);
    ADCIntEnableEx(ADC0_BASE, ADC_INT_DMA_SS0);
    IntEnable(INT_ADC0SS0);

    SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
    SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_ADC1);
    ADCClockConfigSet(ADC1_BASE,ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_FULL, 1);

    ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_TIMER, 1);
    ADCSequenceStepConfigure(ADC1_BASE, 0, 0, ADC_CTL_CH16);        //PK1
    ADCSequenceStepConfigure(ADC1_BASE, 0, 1, ADC_CTL_CH17);        //PK2
    ADCSequenceStepConfigure(ADC1_BASE, 0, 2, ADC_CTL_CH18);        //PK3
    ADCSequenceStepConfigure(ADC1_BASE, 0, 3, ADC_CTL_CH19);        //PK0
    ADCSequenceStepConfigure(ADC1_BASE, 0, 4, ADC_CTL_CH16);
    ADCSequenceStepConfigure(ADC1_BASE, 0, 5, ADC_CTL_CH17);
    ADCSequenceStepConfigure(ADC1_BASE, 0, 6, ADC_CTL_CH18);
    ADCSequenceStepConfigure(ADC1_BASE, 0, 7, ADC_CTL_CH19 | ADC_CTL_END | ADC_CTL_IE);   // ADC_CTL_IE fires every 8 samples
    ADCPhaseDelaySet(ADC1_BASE, ADC_PHASE_0);
    ADCSequenceDMAEnable(ADC1_BASE, 0);

    uDMAChannelAttributeDisable(UDMA_CH24_ADC1_0,
                                    UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST |
                                    UDMA_ATTR_HIGH_PRIORITY |
                                    UDMA_ATTR_REQMASK);

    uDMAChannelControlSet(UDMA_CH24_ADC1_0 | UDMA_PRI_SELECT,
                            UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
                              UDMA_ARB_8);

    uDMAChannelControlSet(UDMA_CH24_ADC1_0 | UDMA_ALT_SELECT,
                            UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
                              UDMA_ARB_8);

    uDMAChannelTransferSet(UDMA_CH24_ADC1_0 | UDMA_PRI_SELECT,
                               UDMA_MODE_PINGPONG,
                               (void *)(ADC1_BASE + ADC_O_SSFIFO0),
                               g_ui8RxBufA[1], MEM_BUFFER_SIZE);

    uDMAChannelTransferSet(UDMA_CH24_ADC1_0 | UDMA_ALT_SELECT,
                                UDMA_MODE_PINGPONG,
                                (void *)(ADC1_BASE + ADC_O_SSFIFO0),
                                g_ui8RxBufB[1], MEM_BUFFER_SIZE);

    uDMAChannelAssign(UDMA_CH24_ADC1_0);
    uDMAChannelEnable(UDMA_CH24_ADC1_0);
    ADCIntEnableEx(ADC1_BASE, ADC_INT_DMA_SS0);
    IntEnable(INT_ADC1SS0);
//--------------------------------------------------------------------
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
    TimerConfigure(TIMER0_BASE, TIMER_CFG_A_PERIODIC);
    TimerLoadSet(TIMER0_BASE, TIMER_A, sysclock/(125000)/*(48000*8*2)*/);
    TimerControlTrigger(TIMER0_BASE, TIMER_A, true);
    TimerEnable(TIMER0_BASE, TIMER_A);

    ADCSequenceEnable(ADC0_BASE, 0);
    ADCSequenceEnable(ADC1_BASE, 0);
}

What could be wrong with my ADC Seq1 DMA configuration????

over 9 years ago

0 Bruno Saraiva over 9 years ago

Guru 13040 points

Hello Sergio,
You might have answered it yourself...
Did you configure any ISR to respond to interrupts on INT_ADC0SS1 on your Startup file?
If you did not, then code will divert to the Default Handler for non-configured interrupts.
Bruno

0 Charles Tsai over 9 years ago in reply to Bruno Saraiva

TI__Guru**** 191886 points

Hi Sergio,
Bruno is correct . You didn't show your ADC ISR. Please make sure you either dynamically create an interrupt registration using ADCIntRegister() or you have the ISR statically registered in your startup_ccs.c file.

0 Sergio Mamani over 9 years ago in reply to Bruno Saraiva

Intellectual 365 points

I was so blind, you were right, thanks Bruno and Charles!!!!

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CCS/TM4C129ENCPDT: Problem with dma configuration for using both ADC