Tool/software: Starterware
Dear all,
I have a problem with spi for two piece TMS570LS0714 communication.
The H/W connect below: one MASTER, one SLAVE. SIMO-.>SIMO ,SOMI->SOMI, CLK->CLK, no others.
The program idea below: Master send data[20] and receive data[20] in 1ms interrupt(HET interrupt, run well).Slave send data[20] and receive data[20] in 1ms interrupt(HET interrupt, run well).
But Master can send data (check register),not receive datas. Slave can no neither. Check Slave register , Flg register is 0x340 means OverRun. When I Clear 0x340 manually and I can see Slave send and receive data just one data, and then FLG is 0x340 .
I don't know how to slove the problem ,please help me.
My code below:
Master:
void _InitSpi3(spiBASE_t *SpiInfo)
{
/* @b initialize @b SPI3 */
/** bring SPI out of reset */
SpiInfo->GCR0 = 1U;
/** SPI2 master mode and clock configuration */
SpiInfo->GCR1 = (1 << 1) /* CLOKMOD */
| 1; /* MASTER */
/** SPI3 enable pin configuration */
// spiREG3->ENAHIGHZ = 0; /* ENABLE HIGHZ *///lugh testtest
/** - Delays */
SpiInfo->DELAY = (4 << 24) /* C2TDELAY */
| (4 << 16) /* T2CDELAY */
| (0 << 8) /* T2EDELAY */
| 0; /* C2EDELAY */
/** - Data Format 0 */
SpiInfo->FMT0 = (63 << 24) /* wdelay */
| (0 << 23) /* parity Polarity */
| (0 << 22) /* parity enable */
| (0 << 21) /* wait on enable */
| (0 << 20) /* shift direction */
| (0 << 17) /* clock polarity */
| (0 << 16) /* clock phase */
| (79 << 8) /* baudrate prescale, 1M Hz *///lugh
// | (7 << 8) /* baudrate prescale, 10M Hz */
| 16; /* data word length */
/** - set interrupt levels */
SpiInfo->LVL = (0 << 9) /* TXINT */
| (0 << 8) /* RXINT */
| (0 << 6) /* OVRNINT */
| (0 << 4) /* BITERR */
| (0 << 3) /* DESYNC */
| (0 << 2) /* PARERR */
| (0 << 1) /* TIMEOUT */
| (0); /* DLENERR */
/** - clear any pending interrupts */
SpiInfo->FLG = 0xFFFFU;
/** - enable interrupts */
SpiInfo->INT0 = (0 << 9) /* TXINT */
| (0 << 8) /* RXINT */
| (0 << 6) /* OVRNINT */
| (0 << 4) /* BITERR */
| (0 << 3) /* DESYNC */
| (0 << 2) /* PARERR */
| (0 << 1) /* TIMEOUT */
| (0); /* DLENERR */
/** @b initialize @b SPI3 @b Port */
/** - SPI3 Port output values */
SpiInfo->PC3 = 1 /* SCS[0] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11); /* SOMI */
/** - SPI3 Port direction */
SpiInfo->PC1 = 1 /* SCS[0] */
| (0 << 8) /* ENA */
| (1 << 9) /* CLK */
| (1 << 10) /* SIMO */
| (0 << 11); /* SOMI */
/** - SPI3 Port open drain enable */
SpiInfo->PC6 = 0 /* SCS[0] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11); /* SOMI */
/** - SPI3 Port pullup / pulldown selection */
SpiInfo->PC8 = 1 /* SCS[0] */
| (1 << 8) /* ENA */
| (1 << 9) /* CLK */
| (1 << 10) /* SIMO */
| (1 << 11); /* SOMI */
/** - SPI3 Port pullup / pulldown enable*/
SpiInfo->PC7 = 0 /* SCS[0] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11); /* SOMI */
/* SPI2 set all pins to functional */
SpiInfo->PC0 = 0 /* SCS[0] */
| (0 << 8) /* ENA */
| (1 << 9) /* CLK */
| (1 << 10) /* SIMO */
| (1 << 11); /* SOMI */
/** - Initialize TX and RX data buffer Status */
g_spiPacket_t[0].tx_data_status = SPI_READY;
g_spiPacket_t[0].rx_data_status = SPI_READY;
/*EmDataRegCfg for EM Config. */
EmDataRegCfg.CSNR = 1;
EmDataRegCfg.CS_HOLD = 1;
EmDataRegCfg.DFSEL = SPI_FMT_0;
EmDataRegCfg.WDEL = 1;
/** - Finally start SPI3 */
SpiInfo->GCR1 |=(uint32)((uint32)1U << 24U); /*SPI3 Enable */
}
uint32 Spi_TransmitAndReceiveData(spiBASE_t *spi,uint32 blocksize,
uint16 * srcbuff,uint16 * destbuff)
{
static uint16 Tx_Data;
uint16 RecvCnt = 0; /*Receive wait time count. */
static uint16 BuffHeaderFlag = 0;/* Receive header data finished flag. */
while(blocksize != 0U)
{
if((spi->FLG & 0x000000FFU) != 0U) /*Error occurs.*/
{
break;
}
Tx_Data = *srcbuff;
spi->DAT1 = (spi->DAT1 & 0xFFFF0000U) | ((uint32)Tx_Data);
srcbuff++;
while((spi->FLG & 0x00000100U) != 0x00000100U)
{
RecvCnt++;
// if(RecvCnt >= 500)
// {
// break;
// }//lugh
} /* Wait */
*destbuff = (uint16)(spi->BUF & 0xFFFFU);
if((blocksize == 20) && (*destbuff == 0xAAAA))//lugh
{
BuffHeaderFlag = 1;
}
if(BuffHeaderFlag == 1)
{
destbuff++;
}
blocksize--;
}
BuffHeaderFlag = 0;
return (spi->FLG & 0xFFU);
}
Slave:
void _InitSpi3(spiBASE_t *SpiInfo)
{
/* @b initialize @b SPI3 */
/** bring SPI out of reset */
SpiInfo->GCR0 = 1U;
/** SPI2 master mode and clock configuration */
SpiInfo->GCR1 = (0 << 1) /* CLOKMOD *///lugh
| 0; /* SLAVE */
/** SPI3 enable pin configuration */
// spiREG3->ENAHIGHZ = 0; /* ENABLE HIGHZ *///lugh testtest
/** - Delays */
SpiInfo->DELAY = (4 << 24) /* C2TDELAY */
| (4 << 16) /* T2CDELAY */
| (0 << 8) /* T2EDELAY */
| 0; /* C2EDELAY */
/** - Data Format 0 */
SpiInfo->FMT0 = (63 << 24) /* wdelay */
| (0 << 23) /* parity Polarity */
| (0 << 22) /* parity enable */
| (0 << 21) /* wait on enable */
| (0 << 20) /* shift direction */
| (0 << 17) /* clock polarity */
| (0 << 16) /* clock phase */
// | (79 << 8) /* baudrate prescale, 1M Hz */
| (7 << 8) /* baudrate prescale, 10M Hz */
| 16; /* data word length */
/** - set interrupt levels */
SpiInfo->LVL = (0 << 9) /* TXINT */
| (0 << 8) /* RXINT */
| (0 << 6) /* OVRNINT */
| (0 << 4) /* BITERR */
| (0 << 3) /* DESYNC */
| (0 << 2) /* PARERR */
| (0 << 1) /* TIMEOUT */
| (0); /* DLENERR */
/** - clear any pending interrupts */
SpiInfo->FLG = 0xFFFFU;
/** - enable interrupts */
SpiInfo->INT0 = (0 << 9) /* TXINT */
| (0 << 8) /* RXINT */
| (0 << 6) /* OVRNINT */
| (0 << 4) /* BITERR */
| (0 << 3) /* DESYNC */
| (0 << 2) /* PARERR */
| (0 << 1) /* TIMEOUT */
| (0); /* DLENERR */
/** @b initialize @b SPI3 @b Port */
/** - SPI3 Port output values */
SpiInfo->PC3 = 1 /* SCS[0] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11); /* SOMI */
/** - SPI3 Port direction */
SpiInfo->PC1 = 1 /* SCS[0] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK *///lugh
| (0 << 10) /* SIMO */
| (1 << 11); /* SOMI */
/** - SPI3 Port open drain enable */
SpiInfo->PC6 = 0 /* SCS[0] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11); /* SOMI */
/** - SPI3 Port pullup / pulldown selection */
SpiInfo->PC8 = 1 /* SCS[0] */
| (1 << 8) /* ENA */
| (1 << 9) /* CLK */
| (1 << 10) /* SIMO */
| (1 << 11); /* SOMI */
/** - SPI3 Port pullup / pulldown enable*/
SpiInfo->PC7 = 0 /* SCS[0] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11); /* SOMI */
/* SPI2 set all pins to functional */
SpiInfo->PC0 = 0 /* SCS[0] *///lugh
| (0 << 8) /* ENA *///lugh
| (1 << 9) /* CLK */
| (1 << 10) /* SIMO */
| (1 << 11); /* SOMI */
/** - Initialize TX and RX data buffer Status */
g_spiPacket_t[0].tx_data_status = SPI_READY;
g_spiPacket_t[0].rx_data_status = SPI_READY;
/*EmDataRegCfg for EM Config. */
EmDataRegCfg.CSNR = 0;
EmDataRegCfg.CS_HOLD = 0;
EmDataRegCfg.DFSEL = SPI_FMT_0;
EmDataRegCfg.WDEL = 0;
/** - Finally start SPI3 */
SpiInfo->GCR1 |=(uint32)((uint32)1U << 24U); /*SPI3 Enable */
}
uint32 Spi_TransmitAndReceiveData(spiBASE_t *spi,uint32 blocksize,
uint16 * srcbuff,uint16 * destbuff)
{
static uint16 Tx_Data;
uint16 RecvCnt = 0; /*Receive wait time count. */
static uint16 BuffHeaderFlag = 0;/* Receive header data finished flag. */
while(blocksize != 0U)
{
if((spi->FLG & 0x000000FFU) != 0U) /*Error occurs.*/
{
break;
}
Tx_Data = *srcbuff;
spi->DAT1 = (spi->DAT1 & 0xFFFF0000U) | ((uint32)Tx_Data);
srcbuff++;
while((spi->FLG & 0x00000100U) != 0x00000100U)
{
RecvCnt++;
if(RecvCnt >= 500)
{
break;
}
} /* Wait */
*destbuff = (uint16)(spi->BUF & 0xFFFFU);
if((blocksize == 20) && (*destbuff == 0xAAAA))
{
BuffHeaderFlag = 1;
}
if(BuffHeaderFlag == 1)
{
destbuff++;
}
blocksize--;
}
BuffHeaderFlag = 0;
return (spi->FLG & 0xFFU);
}
