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TM4C123GH6PGE: GPIO output failure under EFT test

Part Number: TM4C123GH6PGE
Other Parts Discussed in Thread: DRV8412

Hello,

I'm facing a problem when exposing my board to EFT test.

Pin PA4 is configured as output, driving a logic high signal.

When the Electric Fast Transient is injected into the board, the PA4 pin goes low.

After electric noise removal, I attached the debugger to the running target, and discovered

(surprising) that all PORTA A registers are correctly configured, GPIODATA register have a 1 in the relevant position,

but the pin stays low.

Writing a "1" again into the data register has no effect.

The only way I found to recover from this situation is writing a 0, followed by a 1.

But, this cannot be done runtime, to have no glitches.

While improving PCB layout, does anyone knows

a better way to recover the correct pin status.

Here are GPIOA registers values

  • Do you have any means of feedback from the pin output? Can the thing it controls send back some kind of "I'm doing what I'm told to do" signal?
    If so, you could frequently monitor the feedback against the desired status.
    Other idea is that you divert the existing trace into a different GPIO (talk about one extra surgical jumper on an already compromised board...), configured as input, and keeps polling that input pin. If that pin differs from the desired PA4 level, then "reset" PA4...
    Bruno
  • Have you checked the errata? There is (or was) one dealing with fast edges.

    Robert
  • Thanks for your suggestions.
    Having no available pins, I periodically switch the pin to INPUT mode, to read the pin status.
    Then, set to OUTPUT again. If the read value is inconsistent, I toggle the pin low and high.
    The small 100pF capacitance at the input of the other device (btw, the DRV8412 /RESET pin)
    is enough to avoid any glitch.
    Thanks for pointing out the errata: GPIO#10 thoroughly describes what the behaviour under EFT.
    Regards,
    Claudio