TMDXRM46HDK: RM46x HDK not yet successful in FreeRTOS with CAN1 communication

Hi Neil,

It seems you have several on the same or similar topic. Can we close the other threads and focus on this one?

Since you have been using a newer version of FreeRTOS than what is supported in HalCoGen. Can you first try the HalCoGen CAN examples stand alone to insure the drivers are working effecively, then move to HalCoGens FreeRTOS with the same drivers, then on to the more recent version? Seems this approach might be more simple in regard to identifying driver issues vs integration issues.

Also, what tools are you using to debug the CAN bus? Are you using a CANalyzer tool, NI tool, ...?

Do you have the correct terminating resistances in place at each node on the bus? These are required for robust communication as well as twisted pair cabling.

Have you been able to confirm robust communication of other nodes on the bus? You had previously mentioned extended vs standard CAN frames. Has this handling been understood?

What have you used as you acceptance mask? Are you certain it is setup for the intended messages to be received?

It is fine to close the older posts, since I am going to give up on fixing it the way I have been trying to.

I am OK with trying to use an older FreeRTOS version and HalCoGen. Should I install the newest HalCoGen?

I am using a PC with an IXXAT usb can device and a PEAK usb can device.

I have confirmed the communication network wiring and resistance terminators. The network is fine to operate using the firmware of the DEMO tool. I have very high confidence in the CAN network operation from the usb tools and tools.

My question about frames and extended frames relates to work on other hardware where two mail boxes were used to cover both types of RX.

Funny enough, I just minutes ago checked that the masks values in my firmware were all 0x0.

OK, it is Monday. 

Based on comments and discussions in a post with similar issues, I have been able to get the RM46 HDK send and accept CAN1 frames with confirmable results.  These good results were due to using correct [activate],[enable], and [mask] values in HalCoGen 4.6.1.

https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/295120/1032814?tisearch=e2e-sitesearch&keymatch=rm46 can1#pi239031350=2

This is not yet progress in using FreeRTOS, but It is progress I expect to build on.

Good to here, Neil!

Come back to this thread as you progress through the FreeRTOS implementation as questions arise.

Monday after lunch.

Based on comments and discussion in a similar post with similar CAN ISR issues, I have been able to get the RM46 HDK to utilize VIM and ISR settings. These results were due to using correct VIM setting in CanMsg1 and CanMsg2, and enabling Can1_High, Can1_Low, and Can1_IF3.

e2e.ti.com/.../176797

Still not a full success, since I need to bring in FreeRTOS to this evaluation project.

Tuesday.

Added code with base FreeRTOS sample code. Attempts to debug now fail. Here is a verbose debug log, is there a clue as to why the reset occurs?

CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0 due to System Reset
CortexR4: Writing Flash @ Address 0x00008020 of Length 0x00007ff0
CortexR4: Erasing Flash Bank 0, Sector 0
CortexR4: Erasing Flash Bank 0, Sector 1
CortexR4: Erasing Flash Bank 0, Sector 2
CortexR4: Erasing Flash Bank 0, Sector 3
CortexR4: Erasing Flash Bank 0, Sector 4
CortexR4: Erasing Flash Bank 0, Sector 5
CortexR4: Erasing Flash Bank 0, Sector 6
CortexR4: Erasing Flash Bank 0, Sector 7
CortexR4: Erasing Flash Bank 0, Sector 8
CortexR4: Erasing Flash Bank 0, Sector 9
CortexR4: Erasing Flash Bank 0, Sector 10
CortexR4: Erasing Flash Bank 0, Sector 11
CortexR4: Erasing Flash Bank 0, Sector 12
CortexR4: Erasing Flash Bank 0, Sector 13
CortexR4: Erasing Flash Bank 0, Sector 14
CortexR4: Erasing Flash Bank 0, Sector 15
CortexR4: Erasing Flash Bank 7, Sector 0
CortexR4: Erasing Flash Bank 7, Sector 1
CortexR4: Erasing Flash Bank 7, Sector 2
CortexR4: Erasing Flash Bank 7, Sector 3
CortexR4: Verifying Flash @ Address 0x00008020 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x00010010 of Length 0x00007ff0
CortexR4: Verifying Flash @ Address 0x00010010 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x00018000 of Length 0x00007ff0
CortexR4: Verifying Flash @ Address 0x00018000 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x0001fff0 of Length 0x00005860
CortexR4: Verifying Flash @ Address 0x0001FFF0 of length 0x00005860
CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0 due to System Reset

Neil,

I have asked our halCoGen and FreeRTOS expert to have a look at your post as well to see if there is any advice or guidance that can be provided to get you up and running on the version supported in HalCoGen. Hopefully they will be able to reply to you sometime over night since they are located in a different Time Zone.

Thank You.

Here is a different log from the same build (settings were modified but not code)

CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0 due to System Reset
CortexR4: Writing Flash @ Address 0x00008020 of Length 0x00007ff0
CortexR4: Erasing Flash Bank 0, Sector 2
CortexR4: Erasing Flash Bank 0, Sector 3
CortexR4: Erasing Flash Bank 0, Sector 4
CortexR4: Verifying Flash @ Address 0x00008020 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x00010010 of Length 0x00007ff0
CortexR4: Erasing Flash Bank 0, Sector 5
CortexR4: Verifying Flash @ Address 0x00010010 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x00018000 of Length 0x00007ff0
CortexR4: Erasing Flash Bank 0, Sector 6
CortexR4: Verifying Flash @ Address 0x00018000 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x0001fff0 of Length 0x00005860
CortexR4: Erasing Flash Bank 0, Sector 7
CortexR4: Verifying Flash @ Address 0x0001FFF0 of length 0x00005860
CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0 due to System Reset

Perhaps a more informative log!

CortexR4: Erasing Flash Bank 0, Sector 14
CortexR4: Verifying Flash @ Address 0x000F8630 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x00100620 of Length 0x00007ff0
CortexR4: Verifying Flash @ Address 0x00100620 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x00108610 of Length 0x00007ff0
CortexR4: Verifying Flash @ Address 0x00108610 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x00110600 of Length 0x00007ff0
CortexR4: Verifying Flash @ Address 0x00110600 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x001185f0 of Length 0x00007ff0
CortexR4: Erasing Flash Bank 0, Sector 15
CortexR4: Verifying Flash @ Address 0x001185F0 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x001205e0 of Length 0x00007ff0
CortexR4: Verifying Flash @ Address 0x001205E0 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x001285d0 of Length 0x00007ff0
CortexR4: Verifying Flash @ Address 0x001285D0 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x001305c0 of Length 0x00007ff0
CortexR4: Verifying Flash @ Address 0x001305C0 of length 0x00007FF0
CortexR4: Writing Flash @ Address 0x001385b0 of Length 0x00007ff0
CortexR4: File Loader: Memory write failed: The address 0x14059f does not map to a valid Flash Bank
CortexR4: GEL: File: C:\Users\994607\workspace_v7\NeilRM46\Debug\NeilRM46.out: Load failed.
CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0 due to System Reset

Neil,

This usually indicates that either the CCS memory map has been changed via the script files, or the incorrect target configuration has been selected when setting up the debugger/emulator. Can you check this under the target configuration window to make sure it is correct for the device you are using?

I think the memory command files issues are solved, but the core problem still is happening when trying to debug.

CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0 due to System Reset

Thursday Morning update:

After some hours of building and comparing map files for things that works and things that did not work, I was able to debug. I will report back progress on getting can1 enabled FreeRTOS to run.

Thursday Update:

The FreeRTOS timers are not operating as I see in my other build. Is there something in HalCoGen that I must do to support FreeRTOS timers?

Hi Neil,

In HALCoGen we have separate Examples for FreeRTOS and CAN.
Were you successful in making these two work in your board?

FreeRTOS port uses RTI1 module for Timer configuration.

In the HalCoGen example, which function tells me the DLC of a CAN frame that arrives in a mailbox?