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TMS570LC4357: Parity on the AXI peripheral bus

Brian Silverman20
Prodigy 160 points
Part Number: TMS570LC4357

Does the AXI peripheral bus have ECC on the data and/or parity on the control lines?

The safety manual states that "The CPU core contains the built-in ECC generation and evaluation logic for its AXI interface." (in reference to the data lines) and "The CPU core contains the built-in parity generation and evaluation logic for its AXI interface." (in reference to the address and control lines). That doesn't distinguish between the AXI master interface used for access to RAM and FLASH vs the AXI peripheral interface used for access to the peripherals, so I would expect it to apply to both. However, the PP_BUS_ECC bit in the Build Options 1 Register register of the Cortex-R5 core (bit 0 of c15, 0, c2, 0) is set to 0, which according to the Cortex-R5 TRM means "bus-ECC not included on peripheral ports". Which one is correct?

  • 0
    TI__Guru 59540 points
    Hi Brian,

    The TMS570LC43xx MCU is based on the same architecture as the TMS570 Platform architecture that defines an interconnect between the bus masters and the bus slaves. In this case, however, we end up with 2 main interconnects which connect all of the masters and slaves together. Since these two interconnects are separate it creates what can realistically be considered 2 safety islands. One is the CPU safety island and the second the Peripheral Safety Island.

    For the CPU Safety Island, memories and buses are protected by means of ECC on the data path using Single Bit Correction Double Bit Detection (SECDED) scheme. In addition, a parity detection scheme is used on all address and control paths between all masters and slaves. Safety diagnostic logic is also built into the CPU Interconnect Subsystem where all traffic going in and out are checked against their expected behaviors during application runtime. Finally, there is also self-test logic built into the CPU Interconnect Subsystem which can be enabled to diagnose possible faults.

    In regard to the Peripheral Safety Island which includes the Peripheral Interconnect Subsystem to "glue together" the rest of the masters and slaves in the device, diagnostics are by means of ECC or parity protection on the peripheral memories and MPU protection mechanisms.

    To address your primary question, the Peripheral Interconnect does not employ the same ECC and parity mechanism on the bus transactions that the CPU Interconnect Subsystem does. This is evident when comparing the identified safety mechanisms for the CPU interconnect and Peripheral Interconnects in Table A as well.