CCS/TMS570LC4357: Sleep Mode Waiting for Interrupt

Hello,

The SW sequence to enter a low-power mode is described in 2.4.3.1 of SPNU563.

This is sample code I used on LS12x device (Cortex-R4F). Use it as reference only.

You can wake up the device from the sleep mode using GIO/CAN/SCI interrupt.

void Sleep()

{

//1. Program the flash banks and flash pump fall-back modes to be “sleep”.

Flash_Sleep();

systemREG1->GHVSRC = 0x00000000; //clock source 0 (OSC) for GCLK, HCLK, VCLK, VCLK2

systemREG1->VCLKASRC = 0x00000000; //clock source for peripheral async clock1/2

systemREG1->RCLKSRC = 0x00000300; //clock source for RTI1 source

asm( " DSB");

//2. Disable the clock sources that are not required to be kept active.

// A clock source does not get disabled until all clock domains using that clock source are disabled first,

// or are configured to use an alternate clock source.

systemREG1->CSDIS = 0xCF; //clock source 0...7

//3. Disable the clock domains that are not required to be kept active.

// Write to Clock Source Disable Register - CDDIS - to disable the PLL clock source

systemREG1->CDDIS = 0x0

| (uint32)((uint32)1U << 0U ) /* GCLKOFF */

| (uint32)((uint32)1U << 1U ) /* HCLK OFF */

| (uint32)((uint32)1U << 2U ) /* VCLKP OFF */

| (uint32)((uint32)1U << 3U ) /* VCLK2 OFF */

| (uint32)((uint32)1U << 4U ) /* AVCLK 1 OFF */

| (uint32)((uint32)1U << 5U ) /* AVCLK 2 OFF */

| (uint32)((uint32)1U << 6U ) /* RTICLK OFF */

| (uint32)((uint32)1U << 8U ) /* VCLK3 OFF */

| (uint32)((uint32)1U << 9U ) /* VCLK4 OFF */

| (uint32)((uint32)1U << 10U) /* AVCLK 3 OFF */

| (uint32)((uint32)1U << 11U); /* AVCLK 4 OFF */

//4. Idle the Cortex-R4F core.

// Execute ARM instructions with IDLE cycles to trigger CPU clock stoppage

asm( " NOP");

asm( " NOP");

asm( " NOP");

asm( " WFI"); //Wait For Interrupt (WFI) instruction

asm( " NOP"); //after wake-up, will start from this line

asm( " NOP");

asm( " NOP");

asm( " NOP");

asm( " NOP");

asm( " NOP");

}

void Flash_Sleep(void)

{

flashWREG->FBAC = (0x10 << 16) | (0x0F << 8) | (0x0F);

flashWREG->FPAC2 = 0x0;

flashWREG->FBFALLBACK = 0; // Take Bank 0 and 1 to sleep mode

flashWREG->FPAC1 = 0; // Take Pump to Sleep

}

Hello User,

The process should be very similar, but there may be some additional items to take care of. Please review the appropriate sections within the TRM to make sure all concerns are taken care of. Also, note that we do not specify low power currents for the Hercules devices because, although the logic supports these modes, the transistors used within the device are not well suited for low power or stand by modes and this was not a prioritized feature at design time. This is due to a significant amount of current leakage associated with the technology used. Although the devices may seem to have significant power savings in the low power modes at nominal temperatures, voltages and manufacturing process, there is a significant impact of these conditions at hot temps, higher voltage, and a "hot" manufacturing process which exponentially increases transistor leakage.