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TM4C1294KCPDT: Is there some timing difference here?

David Chance
Genius 4775 points
Part Number: TM4C1294KCPDT

Hi there,

I ran into a "strange" problem with my TM4C1294 project. I tracked it for a long time, and still have no found any obvious bug in my codes, so I am seeking help here:

I am using TM4C1294 to acquire data, paced by TiVa's internal periodical timer running off the 120Mhz system clock in both cases below

If I use external ADC (for higher end products), and acquire the data when the timer ISR is called (the max sample rate is below 200K), although there are some understandable jitter in time due to ISR/priority, everything seems working fine, and the sample frequency is what I expect, for example, 20.00Khz (measured by a frequency counter)

If I use TiVa's internal ADC for the lower end product, I let the same timer to trigger ADC sequencer, and acquire the data when ADC ISR is called, now the jitter is gone, but the sampling frequency seems to be off by a fraction, like 19.99Khz

The difference is higher than the tolerance (50ppm) of the master clock.

I wonder if there is a timing difference between the approach of Timer->ADC sequencer->ADC ISR and the approach of Timer->TimerISR->ADC, or maybe I have a hidden bug somewhere in my codes

Thanks!

  • 0
    TI__Guru 72500 points
    I would not expect any difference. Are you starting the ADC in the timer ISR, or using the timer to create an ADC event? (Using the ISR I would expect the same jitter.) You might want to toggle a pin in the timer ISR to measure the sample frequency, or is that what you are already doing?
  • 0
    Guru 117855 points

    I'm not so sure your methods of measurement have been adequately described - and as your possible, "error" is (just) 0.01KHz - do not those "methods" rise in importance?

    It is suspected that you monitor a Timer-triggered GPIO - which commands your (external) ADC - and that GPIO provides your "external" sampling rate.       Is this correct?

    Your measure of the sampling frequency of the MCU's ADC is not described.      I would think that your continuing, "that Timer-triggered GPIO" (usually routed to the external ADC) would serve to confirm the, "Timer's contribution to the internal sampling rate."      (this Timer-generated GPIO signal maintained - even though you employ the MCU's ADC)      You may then place an additional (separate)  "toggling GPIO"  w/in the ADC's ISR - and measure that - as well.

    Via the measure & compare of these 2 GPIO signals (Timer Output and MCU's entry into ADC's ISR) - any variation - should stand (well) revealed and the source nicely identified)

  • 0 in reply to Bob Crosby
    Genius 4775 points
    Yes, I am toggling a pin to measure that.
  • 0
    Guru 27665 points

    Nice summary but more detail necessary to start tracking it down.

    David Chance said:
    If I use TiVa's internal ADC for the lower end product, I let the same timer to trigger ADC sequencer, and acquire the data when ADC ISR is called, now the jitter is gone, but the sampling frequency seems to be off by a fraction, like 19.99Khz

    Details? I can certainly see simple affects that could give you this kind of error. Either on the timing or the measurement of the timing.

    David Chance said:
    The difference is higher than the tolerance (50ppm) of the master clock.

    For instance have you verified this? Depending on how you are deriving the clock it could be pulled away from its normal centre. Also, since you are using a PLL you need to check its specification.

    Robert

  • 0 in reply to David Chance
    Guru 27665 points

    David Chance said:
    Yes, I am toggling a pin to measure that.

    I would expect that to be different from the A/Ds sampling. More jitter but I would expect the average to approach the actual rate.
    Your 'scopes accuracy and precision will come into play here as well.
    Robert
  • 0 in reply to Robert Adsett
    Genius 4775 points
    I verified the frequency with a frequency meter, not scope, with 10 second window
  • 0 in reply to Robert Adsett
    Genius 4775 points
    Since no one heard of any hard ware bug, I will drive both design with a fixed 25Mhz external clock to see if I can observe the result
  • 0
    Guru 27665 points

    David Chance said:
    have no found any obvious bug in my codes,

    Key word highlighted.

    And since you appear reluctant to share, it makes it even more difficult.

    Robert

  • 0 in reply to David Chance
    Guru 27665 points
    Frequency meters are not immune to precision and accuracy concerns.

    Robert