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RM48L952: N2HET: het1 pin 27 edge is not detected by n2het program (no IRQ), het1 pin26 edge is detected also by pin27 monitor (gives IRQ from wrong pin)

Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

Hello,

We are having another N2HET related problem which can be reproduced with TMDSRM48HDK kit (S2 switches all OFF). We have exactly similar issued with our new HW where one pin was changed from GPIO port to HET1 pin 27. NOTE: edge (pin up state) is long enough HET to detect it in real hw, we have redundant feature where other pin is (and has been there already in previous HW) connected to HET 1_14 pin and it gives IRQs without problems and 1_27 doesn't give when old HW gpio-port worked without problems. Initially though this to be circuit board issue in new HW but since DIN shows the pin state correctly the connection is good.

See attached project. If you run it with "#define TEST_PIN26    1" (line 132) - rising edge to pin26 is made - the HET detects edges also in pin 27 (see 'au32HetIrqs' content when while(1) reached). If you run it with "#define TEST_PIN26    0" - rising edge to pin 27 is made - the HET does not detect any edges.

DIN shows that targeted pin has really gone up and others are down... In this demo we just control that pin by ourselves which het monitors but in real life we have real input source connected to that pin and have exactly same problems (controlling itself works as well since input is monitored), HET doesn't signal IRQ when monitored pin 27 goes up and if we control out pin26 (which is output in real life for something completely separate thing) the IRQ will be generated also to pin 27....

HET 1_27 pin is a bit special it has direct ball A9 and muxable ball B2 (well mux is not directing B2 to HET), similarly  has HET 1_29 (A3 & C3) and HET 1_31 (J17 & W9) pins. The common for all these was that IRQ is not signalled if A9, A3 or J17 goes up. Didn't test to control 1_28 or 1_30 if these generates irqs to 1_29 & 1_31 like 1_26 generates to 1_27. Also 17, 19, 21, 23 and 25 have similar 2 pin connection possibility but haven't tested those...

Could find anything from TRM nor data sheet that those pins/het ports are "special" and they should be used differently... I understand that some problems may occur if muxable pins are also routed to HET but that should be the case in the demo nor in our real hw, only the fixed pin should go to the HET.

Errata mentions some problems with PCNT when measuring the pulse lengths, since HR is not used at all and only IRQ is wanted those errata findings should not have any effect (and demo application fails similarly also if PCNT's are removed completely from het code & application side)...

We have tried both ECNT and PCNT HET instructions to give IRQs in rising edge but both works similarly, in the demo project both are used simultaneously and all irq's are counted together and also separately per offset to verify that irq count read from array slots via debugger matches total count. I also put "dummy" delay after irq enable and before edge generation to be sure that if code is stopped before edge making the HET have had enough time to run 1 round (this should be useless, but it is there just in case).

Can you find some errors from code? Or is those ... 27, 29,31 het pins somehow special and cannot be used as we would like to use? Why edge in pin26 is catched by het-code in monitoring instruction for pin27 when DIN shows that pin27 is down and 26 is up...
 

Here is the project which re-produces the situation (again tested with 2 HDKs, 2 different computers & geographic location), all "application" code is in sys_main.c. Application just intializes het, enables IRQ, puts pins 26&27 down, enables HET IRQs (clears possible pending irq from that offset)) for targeted offset lines and then makes rising edge to either pin 26 or 27.
8875.N2HET_irq_problem.zip




  • This looks to be caused by default HalCoGen settings for N2HET pins? HR share is enabled in Pin 0-7 and Pin 24-31... After I turned HR share off for pins 26&27 the IRQs are detected as expected... Rather annoying feature since default value for share register in CPU is all OFF and HalCoGen changes that...
  • Jarkko,

    Sorry for the inconvenience here. I have sent you post to our Halcogen lead to check if there is a reason for this and it is intentional or not. If not intentional, I will open a ticket on it.
  • Hi Jarkko,

    The moment you use HALCoGen based Init functions, it is given that user has reviewed all the GUI related settings. HALCoGen never claims the default register value are maintained, it is users responsibility to review the GUI configuration, and remove if some configurations are not required for them. .
  • I kind of agree with you, but since it looks like that only some pins are altered and some doesn't this seems more like a "goofy setting" than deliberate action of the GUI.

    I would buy the GUI settings if every pin would be either on or off consistently by default (off more likely in this case since there shouldn't be any reason to expect that "hey, they most likely want to share than pin - let's do it for them". The reason for this "goofy setting" might be "default het code" so that it uses those pins with such config. But in case user selects "enable advanced config" the setting possibly made for "default het code" purposes should be undoed to enhance the user experience.
    - This is first HalCoGen config which I have encountered as "non-rationale" in this way so my guard was down for this kind of behavior, for example all VIM channels are set as IRQ by default not IRQ/FIQ/IRQ/FIQ...

    I wouldn't have made that thread if I would have find the reason by myself, I was all the time pretty sure that mistake is somewhere in my code/settings but since having spend too many hours to find it, deciding to ask it while continuing error hunting since I was pretty sure that from demo application the error can be pointed out immediately. While initially seeking the error I am pretty sure that I also tried that HR share but most likely turned it off accidentally from 28&29 pair- big mistake, since after that I had basically eliminated that possibility in my mind. Second mistake was to not try that again with "demo code" since real application may have had also some other failure which prevented that irq from coming in that try even correct pin would have been selected from HR share...

    I looked also HETHRSH register description - from that at least I couldn't see then&now that het code is not capable of handling that input at all since only HR was mentioned and I didn't use it (high resolution) in instructions.

    After I figured what is wrong I usually try to re-seek that also from TRM - just to learn what I haven't noticed or understood. But this is still something what is difficult to understand for me, maybe it is the term "HR" which confuses/ed me.

    TRM 20.2.5.3 as well as 20.1.1.2 basically mentions that HR is helping to overcome the LRP limitations in signal measuring/generation
    - I have assumed so far (and still based on purely from TRM text) that if HR is not enabled in instruction this HR stuff is more or less meaningless for you - wrong assumption

    TRM 20.2.5.5 does not say that directly either, it offers multiple tips which combined you can quite easily come to a conclusion that het code cannot read/handle the pin at all if HR share is enabled despite do you use HR resolution feature in instructions or not, but since you have already built that wrong assumption it is rather tricky to overcome it just by reading the text.


    What I am trying to say that even if you "review" the setting you may not find the error. Afterwards thinking the pin 26 "visibility" in pin27 instruction should have rang the bell earlier but since haven't done much het code it didn't... And HalCoGen code which was used has been generated months ago (for example I activate the HET offset IRQs in application not from GUI since minor het code change changes offsets resulting GUI based activation keeping wrong offsets activated) and that generated code have worked without problems so far (since those odd-pins has not been used in het code) that HR share was quite well hidden from that perspective also...

    Well this wasn't first time (and won't be last) when everything is depended on 1 wrong bit in register - the problem will always be just to find that bit...