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TM4C1292NCPDT: Simultaneous uDMA usage for peripherals

Balasubramani C
Expert 1685 points
Part Number: TM4C1292NCPDT

 Hi,

TM4C1292NCPDT is having uDMA supporting 32 channel. I have found in datasheet that its having only one DMA interrupt source number.

 

I want to use uDMA for two different peripherals(ADC & DAC via SPI interface). How can we define ISR handler for two different peripherals(ADC & DAC via SPI interface) using DMA operation? I believe that DMA will switch the operation among the peripherals based on priority defined. If so how DMA interrupt handler will be identified in Software for different peripherals?

Regards

Bala

  • 0
    Guru 13040 points
    The interrupt that handles the end of a DMA transfer is the interrupt assigned to the original peripheral, not the specific DMA ISR.
    These DMA interrupts are only used if you want to monitor something specific to the DMA engine, but that is not usually needed.
    Further, remember that you only need to create one interrupt array control variable (with aligned 1024 bytes), not one for each peripheral.
  • 0 in reply to Bruno Saraiva
    Expert 1685 points

    Bruno Saraiva said:
    The interrupt that handles the end of a DMA transfer is the interrupt assigned to the original peripheral, not the specific DMA ISR.
    These DMA interrupts are only used if you want to monitor something specific to the DMA engine, but that is not usually needed.
    Further, remember that you only need to create one interrupt array control variable (with aligned 1024 bytes), not one for each peripheral.

    Hi Bruno,

    Let me explain my requirement clearly. I have configured External ADC via one SPI interface and External DAC via another SPI interface. now I want to configure uDMA in ping - pong mode to receive the 512 samples(16 bit per sample) continuously from ADC via SPI and generate the interrupt to the processor after buffer getting filled. At the same time, i want to send 512 samples(16b bits per sample) from memory buffer to DAC via SPI interface and need to generate the interrupt to the processor after buffer gets empty.

    My question is how can we define interrupt source for these two ISR handlers when its running simultaneously?

    Regards

    Bala

  • 0 in reply to Balasubramani C
    Guru 13040 points
    I don't actually see a "interrupt" specifically for DMA. The only thing on the Tivaware UG is the uDMAIntStatus, to inform which channels have DMA interrupts set.

    We never used SPI transfer with DMA, but I'd assume that it will trigger the SPI interrupt once the whole cycle is finished. Have you tried?

    Did you go one step back, and try a software-controlled transfer of a 512-words SPI transfer?
  • 0
    TI__Guru**** 191206 points
    Hi Bala,
    In the DMA interrupt ISR you can call uDMAIntStatus to find out which DMA channels have generated the interrupt. You will then prioritize which channels to service accordingly.