• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 31 subscribers
  • Views 860 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Compiler/TMS570LS0432: How to observe data in SPI Master_Slave HalCoGen example?

Xinyu Wang
Intellectual 845 points

Part Number: TMS570LS0432
Other Parts Discussed in Thread: LAUNCHXL-TMS57004

Tool/software: TI C/C++ Compiler

Hi, TI Engineer

When I use SPI Master_Slave example to test the LAUNCHXL-TMS57004, I can not observe the data directly in CCS. Is there any way to observe data directly in CCS? And I really want to know how to use SpiRxStatus(). I think it could help me to know in which process SPI communication stay. 

Thanks and regards!

Xinyu 

  • 0
    TI__Guru**** 199546 points
    Hello Xinyu,

    SpiRxStatus() is used to check the status of the receiving data block: SPE_READY, SPI_PENDING, SPI_COMPLETED. It is used in interrupt mode.

    If you want to use the SPI_master_salve example code, you need to configure SPI as master and SPI2 as slave, connect SPI1 signals and SPI2 signals with wires. Also you need to enable the SPI2 interrupt (VIM channel 17 or 30).

    PIN Connections must be as Below
    ---------------------------------------------
    SPI1 ( Master ) SPI2 ( SLave)
    ---------------------------------------------
    SIM0 ---> SIMO
    S0MI <--- SOMI
    CLK ---> CLK
    CS0 ---> CS0

    After run the code, you will see the data in RX_Data_Slave, and RX_Data_Master.
  • 0 in reply to QJ Wang
    Intellectual 845 points
    Hello, Wang

    I should enable SPI2 Level 0 or Level 1 channels. But in the example, I should enable SPI2 Level 0 and Level 1 channels. Which one is good for testing SPI communication. And following steps of the example, I can not see the data in RX_Data_Slave and RX_Data_Master. I am so confused.

    Thanks and Regards!

    Xinyu
  • 0 in reply to Xinyu Wang
    TI__Guru**** 199546 points
    Hello Xinyu,

    The SPI module has two interrupt lines, level 0 and level 1, to the vectored interrupt manager (VIM) module. Two offset registers INTVECT0 and INTVECT1 determine which flag triggered the interrupt. Each interrupt also has a bit that can be set as interrupt level 0 (INT0) or as interrupt level 1 (INT1). Level 0 has higher priority than level 1.

    You can use either level 0 or level 1.