RM57L843: some MCU Architecture Questions about TCM

Hello Canfodersijii,

canfoderiskii said:

• Does the L2SRAM use the port for A TCM?
• Does the Flash use the ports for B TCM?
  1. From the MCU block diagram, I can see Flash uses two ports, so are they using the B0TCM and B1TCM?

The RM57xx device uses a cache configuration and TCM is no longer used. The SRAM and Flash are now co-located on the CPU interconnect subsystem. The ATCM and BxTCM are no longer used.

canfoderiskii said:

From the ARM Cortex-R programer's guide,  there is a section comparing the performance between cache and TCM. Does it imply that the TCM is accessed directly without cache operation?

1. so if the L2SRAM and flash are connecting R5F core via TCM ports, are they cached?

This comparison is provided since the cache is now used for immediate accesses compared to the TCM previously. The L2SRAM and L2Flash are not connected via TCMs.

canfoderiskii said:

I also checked the datasheet and TRM for RM48. Both the document mentioned the details of  the relationship between TCM and Flash or TCM and L2SRAM. But why the details like that are omitted in the document of RM57? Does the implementation changes a lot?

Yes, the implementation does change since there is now the CPU interconnect subsystem and the peripheral interconnect subsystem. The CPU Interconnect subsystem is used for access to the SRAM and Flash and manages priorities amongst masters between CPU and other masters CPU, DMA, HTU, etc.Section 2.1.1 does a fairly decent job of explaining the interconnect on the RM57.

canfoderiskii said:

So on RM57 the L2SRAM, Flash and SDRAM all can be cached in L1, if those region is configured as Normal type in MPU?

Yes. That is a correct.