• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 30 subscribers
  • Views 1001 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137: worst case bus throughput, latency

Wayne Padgett
Prodigy 90 points
Part Number: TMS570LS3137

I am trying to analyze bus performance in the TMS570LS3137 device, particularly to determine how predictable bus throughput and latency are. I have a fair idea of how to determine worst case scenarios, for example, what other accesses could slow down the CPU reading a block of data from RAM and by how much. But, I'd like to be more certain, and I'm not sure I've found all the details available on things like which crossbars I need to consider, which devices participate in the round-robin list for the VBUSM-SCR, whether switching happens after every access (or can a master hold the bus for more than one access), and which competing masters might take the longest to complete an access. Is there an application note or other document that put these details together in one place?

  • 0
    TI__Guru 59540 points
    Hello Wayne,

    The RAM and Flash memories on the device are connected directly to the TCM interfaces of the Cortex-R4F so more information should be able to be found within the ARM technical support for accesses related to the TCM. For the other peripheral accesses and conflicts with the masters, the block diagram that is in the datasheet should give a highlevel view of the various SCRs/crossbars that are used. Generally speaking, the modules listed on top tend to be the additional bus masters that need arbitration in the system and to which the priority scheme is applied.

    Architecturally, I am not aware of any additional documentation other than the TRM and datasheets that go into anything close to what you are looking for. I will check with some other team members and some of our former design team members to see if any additional material exists that can be shared.
  • 0 in reply to Chuck Davenport
    Prodigy 90 points

    Thanks Chuck,

    Any additional documentation you can provide would be very helpful.

  • 0 in reply to Wayne Padgett
    TI__Guru 59540 points
    Hello Wayne,

    Unfortunately, we are lacking in this level of documentation. The best information in this regard is located in the TRM in chapter 2.1 that discusses the architecture.