- In the ARM document DEN0042A(ARM Cortex-R Series Programmer's Guide version 1.0), the section about cache write policy, it says:
- The Cortex-R5 processor also uses write-through so that uSCU can maintain coherency between L1 cache and the master connected to the ACP.
- In the document DDI0460D(Cortex-R5 TRM r1p2), section '9.8 Accelerator Coherency Port Interface', It says:
- The Cortex-R5 ACP memory coherency scheme only provides coherency between an external master connected to the ACP slave port and a CPU with a data cache in the Cortex-R5 group for memory regions configured as inner cacheable write-through in the CPU's MPU.
- In the MCU datasheet(SPNS215C), section 'Summary of ARM Cortex-R5F', it says:
- AXI accelerator coherency port(ACP) supporting IO coherency with write-through cacheable regions.
Questions:
- Does the information listed above imply that I should configure certain part of L2SRAM or SDRAM as Normal, inner write-through region, if that part is to be shared with DMA , HTU, or something else?
- If I configure some region as write-back, then does the ACP is totally skipped for that region and then software cache maintenance must be used?
- The ESM module's channel 47 is 'ACP d-cache invalidate'. What does it mean? How can it occur?
- Does it mean it's when some region is configured as write-back and the corresponding cache line is dirty, whose content is not coherent with the data updated by external master (like DMA) via ACP?
- Or does it mean it's happening when some region is configured as write-through and external master update some content in RAM,after wihch the d-cache invalidating operation is automatically taken but failed?
