CCS/RM46L852: MibSPI transfer-ready interrupt not working

Tool/software: Code Composer Studio

Hello,

I have configured a TG of 4 buffers that is doing what it should (send 1 byte as command and receive 7 bytes of data to/from an acc sensor) when it is triggered via SW:

while(1) {
    delay(15); // faster than the sensor's data rate
    mibspiREG5->TGCTRL[3] = (3*TG_STARTBUF) + TRIG_SW + ONESHOT + (uint32)TGENA;
    while ((mibspiREG5->TGINTFLG & 1<<(16+3)) == 0) ; // wait for transfer-completed flag
    echoAccDataViaSCI(); // got it
}

The sensor is configured to emit an interrupt on new data. With the readout still timed using a delay loop, I see the signal rising on new data and falling on readout as expected. The following code lets the MibSPI use it:

gioREG->GCR0 = 1; // GIO module out of reset
gioPORTA->PULDIS = 1<<7; // INT1 pin of acc sensor is push-pull by default
mibspiREG5->TGCTRL[3] = (3*TG_STARTBUF) + TRIG_GIOA7 + TRIG_RISING + (uint32)TGENA;

Works well, tested by a modified loop body:

while(1) {
    while ((mibspiREG5->TGINTFLG & 1<<(16+3)) == 0) ; // wait for transfer-completed flag
    mibspiREG5->TGINTFLG = 1<<(16+3); // clear that flag
    echoAccDataViaSCI();
}

Then, instead of the loop body, I registered the following ISR in sys_vim.c (at both levels, idx-1 = 53, 56):

int test = 13;
#pragma INTERRUPT(mibSPI5ISR, IRQ)
void mibSPI5ISR(void) {
    mibspiREG5->TGINTFLG = 0xffffffff; // clear flags
    test = 42;
//  basic statistics on acc-sensor datagrams
}

and enabled the interrupt:

mibspiREG5->TGITENST = 1<<(16+3);
_enable_interrupt_();

but test (at file scope) keeps at 13. What is missing?