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TM4C1292NCPDT: SPI and uDMA operation clarfication

Balasubramani C
Expert 1685 points
Part Number: TM4C1292NCPDT

Hi,

My goal is to achieve the uDMA operation through SPI interface to read the samples continuously from LTC2333-16 ADC without much micro controller intervention.

Through TM4C1292NCPDT datasheet we understood that uDMA is possible with SPI interface. i.e SPI will issue DMA request whenever SPI data buffer gets filled. uDMA will be configured in ping-pong mode to receive the data from SPI to memory and generate the processor interrupt whenever uDMA ping/pong buffer gets filled.

LTC2333-16 ADC has an option for configuring control words i.e pre-determined order for channel selection in sequence mode of operation. However CNV i.e. convert signal is required for each channel to start the conversion from master. BUSY signal de-assert when conversion is complete and expecting SCKI signal from master to drive SDO data. Please look at the timing diagram for single sample below.

 

To use the internal sequencer of the LTC2335-16, we have to program it as described below with the desired sequence of up to 16 configurations. Each of these configurations specifies the desired channel number and SoftSpan range for one conversion. The LTC2335-16 will then apply the first configuration to the first conversion, the second configuration to the second conversion, and so on until the end of the programmed sequence is reached, at which point the cycle will start again from the beginning.

 

Now i have plan of using Timer pulses for handling CNV signal for each sample. However SPI should have some kind of handshake signal between ADC BUSY signal and drive the Master clock without processor intervention.

 

Please clarify the following. 

  1. Should SPI capable of handling BUSY signal to drive the master clock to ADC without processor intervention for every sample read?
  2. Please suggest if any logic can be implemented to handle the handshake between BUSY signal and SPI master clock.
  3. Is it possible to give some signal from uDMA to ADC after every sample read from SPI buffer without processor intervention?

Thanks

Bala

  • 0
    TI__Guru*** 135355 points
    Hello Bala,

    1) No, the SPI should and would not be capable handling the BUSY signal without the processor controlling it to do so
    2) Have a GPIO w/ interrupt on the BUSY pin and when it drops low then queue the SPI bus to begin communication to read out the ADC result
    3) There is no signaling capability from uDMA to the external ADC. However, it could be maybe possible to setup another DMA channel to that you could perform DMA transfer from the RAM to the GPIO. Then you could use the GPIO signal to signal the external ADC? This isn't exactly an efficient method though as neither the DMA nor the CPU can do bit writes so you probably would be better off trying something like outlined in answer 2.
  • 0 in reply to Ralph Jacobi
    Expert 1685 points
    Thank you Jacobi.
  • 0 in reply to Balasubramani C
    Expert 1685 points
    Hi Ralph Jacobi,

    one more question.

    it seems that the fundamental problem is that the ADC does not source the serial communication bit clock, so the most direct communication implementation would make the CPU a SPI master. But, SPI masters are designed to transfer messages continuously.

    Configured as a SPI slave, can the SPI interface on the TI uP accept a clock input that is irregular?

    If so, then adding digital hardware that generates the serial clock and gates it to run only during the data transition window would allow use of the normal SPI DMA in both directions i believe. please clarify.

    To configure the sequencer mode operation of ADC, the TI uP SPI needs to be set in Master mode; would it be possible to change the SPI configuration to Slave in run time after configuration?

    Will the TI processor’s SPI wait to read the next data – until the clocks resume after next conversion? will SPI slave received date DMA to memory buffer without processor intervention?

    Regards
    Bala
  • 0 in reply to Balasubramani C
    TI__Guru*** 135355 points
    Hello Bala,

    While I didn't read your ADC datasheet in great detail, what I did read sounds like it is meant to be only a slave device when operating via SPI (see Pin functions on Page 14... specifically pin function for SCKO).

    With that knowledge in mind, you should be only concerning yourself with using the TM4C as a SPI master.

    You said that SPI master are designed to transfer messages continuously - I am not sure I understand what you trying to convey in this case? Can you clarify this better?
  • 0 in reply to Ralph Jacobi
    Expert 1685 points
    Hi Ralph Jacobi,

    Let me explain clearly on my queries.

    I want to read the 24bit data from LTC233-26 ADC via SPI interface continuously i.e using DMA without processor intervention. from LTC datasheet i understood that its required CNV signal and SCKI from SPI master for sending SDO data after BUSY signal transition from high to low. in this case i am planning to add some external hardware circuitry to control the CNV signal and provide the clock to ADC after BUSY signal alert.
    1. if i configure TI micro controller SPI as slave device with external clock, will uP SPI slave able to receive the from ADC which clock is irregular?
    2. is it possible to set the DMA data transfer while SPI in slave mode?

    Regards
    Bala
  • 0 in reply to Balasubramani C
    TI__Guru*** 135355 points
    Hello Bala,

    1) In general this should be okay because what matters is the edges for clocking in data. That said, you need to be careful that the period does not get too small. The TM4C12x devices cannot have SCLK to the slave higher than 1/12 of the system clock, so therefore the clock cannot have periods of time that exceeds this limit. Other than that, it should be okay, but by having an irregular clock you may be adding a lot of complexity as far as debug is concerned as you have to make sure the frequency stays within the aforementioned range. For full understanding of Slave mode timing, see the specs on Section 27.17 of the device datasheet (one of the notes includes the mention of the 1/12 SysClk requirement).

    2) Yes, this is possible to do. If you are not sure how to do this, search the E2E forums for "SPI Slave DMA" - many queries have been made on this topic and there is a lot knowledge available for you to browse through! :)