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RM48L952: EMIF ASYNC extra pulses

Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

Hello!

It seems that there are a lot of discussions ongoing about EMIF ASYNC extra pulses.

RM48L952 Rev.D Errata says that these can be fixed with MPU region definition device or strongly ordered.

My config:

With this configuration extra pulses are still there.

So I would like to know:

1) How to check if these region settings are really in use. Example if other region might overlap with region 5. I checked that I really call mpu init function.

2) In another E2E thread, TI employee said that with another MCU this fix is not enough and you need to externally OR EMIF_nOE signal with DQM signals to get rid of extra pulses. So is it possible that there is an error in RM48L952 Rev.D Errata? Should Rev.D Errata say also that please do the external OR with EMIF_nOE?

Br,

Toni

PS. I tried this external OR and it seems to work, but it slows EMIF ASYNC throughput...

  • Hi Toni,

    The workaround for EMIF#4 is to configure the external memory region in MPU as "device" or "strongly ordered" type. The HALCoGen shows the start address and end address of all the MPU regions, it is pretty easy to check if any regions are overlapped.

    Can you please give me link of hardware workaround (OR with nOE)? I know another device has similar workaround for new, but not RM48.
  • Hello!

    Link to that thread: e2e.ti.com/.../1882079

    Yes, I can see MPU regions from Halcogen configuration, but in example if I would not call mpu init, then these regions would not be in use. So I would like to check configuration with debugger while running code.

    It seems that this is possible, but difficult. This is because MPU is a co-processor and one needs to use MRC-instruction to fetch stuff from there.

    Br,
    Toni
  • Hello Toni,

    That workaround (OR with nOE) is for RevB TMS570LC43x device and RM57 device. The only workaround for RM48 EMIF#4 is to use device mode or strongly order mode which are configured in MPU. I am sorry for the inconvenience.