Other Parts Discussed in Thread: TMS570LS3137
Hello
Our plan at present is to set HCLK = VCLK = 110MHz.
The guidance on current consumption when the clock frequency is reduced assumes HCLK = 2 × VCLK which does not cover our case.
Do you have a model for power consumption that will cover our case. If the model includes the effects of enabling and disabling the various functions as well that would be great.
Many Thanks
Bob Bacon