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RM41L232: When does the GR3.7 ESM error occur

lina zhang
Intellectual 440 points
Part Number: RM41L232

Hello,

I have integrated SafeTI to my system. In our system after poweron I run SL_SelfTest_SRAM(SRAM_ECC_1BIT_FAULt_INJECTION,TRUE,&sram_stResult) and found that the result of this funciton was always FLASE.

Then I entered this function and found that the program exited from the following return statement.

/**********************************************************************************/

    /* If nERROR is active then do not proceed with tests that trigger nERROR */
    if(SL_ESM_nERROR_Active()){
        SL_Log_Error(FUNC_ID_ST_SRAM, ERR_TYPE_ENTRY_CON, 3U);
        return(retVal);
    }

/**********************************************************************************/

After retun I read esmReg->SR[2] and it was 128 that means GR3.7 error has occurred.

so I want to know when the GR3.7 ESM error occurs and how to solve this problem.

Please help, and Thanks.

  • 0
    TI__Guru**** 197036 points
    Hello Lily,

    As the device is coming out of the device reset sequence the flash wrapper reads two configuration words from the TI OTP section of bank zero. During these reads ECC is enabled. Single bit errors are corrected and uncorrectable errors will generate an ESM group 3 channel 7 error event. The ERROR pin will be activated.

    Power on reset (PORRST) will clear the bit in ESMSR3. You can manually write 1 to channel 7 bit in group 3 related registers (status SR3/EPSR, etc).