TM4C1292NCPDT: QSSI Freescale mode, enhanced mode timing

Hello,

Restating the questions:

Section 17.3.4 of the data sheet states that the SSInFss signal can be programmed to assert low at the start of each frame for enhanced modes of operation.  This raises a few questions:

Are 'advanced SSI mode' per section 17.3.3  and 'enhanced  modes'  per section 13.3.4 the same?

If so, then how does it differ from legacy mode with an 8 bit frame?  In particular, the FSSHLDFRM bit of register SSICR1 does not appear to require that the MODE field be set to a mode other than legacy for SSInFss to be pulsed once per frame.  In general, how does legacy 8 bit mode differ from advanced SSI mode with 8 bit packet size? Section 17.3.7.3 describes ‘Freescale SPI Frame Format with SPO=0 and SPH=0’. What difference does legacy versus Advanced mode make for this frame format?

Looking at firgure 17-5, in datasheet section 17.3.7.3,  timing for Freescale SPI format, the bit clock SSInClk stays low for more than a half clock cycle between frames.  But, no specification seems to give its exact timing, nor the relationship to SSinFss. The text below the figure describes the timing, but ambiguities remain.  What specification describes SSInClk timing and SSInFss timing for Freescale SPI format with SPO=0 and SPH=0?

"Advanced SSI mode" is different from "enhanced modes". The advanced SSI mode is a subset of the "Legacy mode" but it allows switching to "Bi" or "Quad" mode. Legacy mode does not allow you to "switch on the fly".

For your next question I will need to do some measurements tomorrow. (I am off-site today.) To be clear, your question is what is the delay between the last clock of one frame and the first clock of the next frame, and the timing of SSInFSS for Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0, assuming the TX FIFO is not empty. Did I understand correctly?

Yes, you understood my question correctly, and accurately restated my question.  But my goal is to get accurate frame cycle timing for Freescale SPI format, continuous transfer , SPO=0, SPH=0.  This way of stating the question differs slightly from the original statement, but the two arrive at the same result.

From the available information, figure 17-5 of section  17.3.7.3 of the TMC4C1292 user's manual does not fully specify the serial bus timing.  The figure contains vertical lines indicating serial clock periods, but the drawing shows a longer clock period while SSInFss is high, and possibly a shorter clock period during the immediately previous period. 

Looking at an entire frame during Continuous Transfer, what is the time in terms of SSInClk cycles from one reference transition of SSInFss, say the falling edge, to the next reference transition?

Saying a bit about my application, it will use one SPI channel to read and control an ADC, using one edge of SSInFss for as the sample and conversion command signal.  So accurately knowing cycle timing is critical.

Thank you,

M.Reich

Hello,

Some additional speculation and questions.

The attached figure shows three reasonable timing variations  for figure 17-5. 

The second variation looks most like the figure in that sSInFss remains a half clock cycle long, and the interval between  is 1.5 clock cycles.  But this implementation would require that the SPI master invert the phase of SSInClk with respect  to the underlying clock at every frame.

The first variation has a 1 clock cycle between the LSB of frame n and the MSB of frame n+1.  This would leave only a half clock cycle between the falling edge of SSInFss and the rising edge of the next clock, contrary to figure17-5 and the text describing the first word of a transmission.  SSInRx could not be driven earlier then SSInTx, also contrary to the figure.  But this variation does not require clock phase inversion.

The third variation also does not require clock phase inversion, and preserves the most features if the timing in the figure by having two clock cycles between LSB of frame n and the MSB of frame n+1.  However, this requires more time between frames than the figures seem to show.

Is the level of SSInRx Q (unknown) between frames, per figure 17-4?

Is the level of SSInTx logic low as figures 17-4 and 17-5 seem to show.

TMC4C1292NCPDT_Figure 17_5_variations.pdf

Hello Bob,

Do you have any information on the Freescale format continuous frame timing questions?

Thank you,

M.Reich

Hello Bob,

Have you had a chance to measure the SSInFSS timing?