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RM57L843: Privileged mode in NMPU access permission

eric
Intellectual 885 points
Part Number: RM57L843

Hi,

Could anyone explain that how to use the privileged mode in the NMPU setting?

As I know, the EMAC or DMA run in the user mode, why there is an access permission control for privileged mode?

  • 0
    TI__Guru 59540 points
    Hello Eric,

    User and privileged modes are dependent on the system settings and not related directly to the bus masters themselves. i.e., you application can operation in user mode only which allows certain level of restrictions based on the NMPU AP setting. If you switch the mode to privilege mode (at system level) the bus master would have a different level of access based on that same AP setting. This allows some supervisor type operation in your application and is effective, for example, when initiating tasks in an RTOS where some tasks may have higher permission levels than others.
  • 0 in reply to Chuck Davenport
    Intellectual 885 points
    Hi Chuck,

    Can I understand like that the DMA (a bus master) access internal ram depends on the CPU core's mode?
    The NMPU of DMA which is configured as privileged WR, user No-access is able to write/read the ram only when the CPU core is in privileged mode? If the CPU core is in user mode then an violation error of NMPU is generated?

    The DMA should runs independently with CPU core to improve the core's thoughout, if the core's mode limits the DMA i think the performance will be poor.
  • 0 in reply to eric
    TI__Guru 59540 points
    Hi Eric,

    I double checked my interpretation on this and my original statement was incorrect. The TRM chapter and AP setting definitions listed in the register description table are generic. This means that they are defined in such a way that will support both privilege mode and user mode accesses. However, you original comment regarding the non-CPU bus masters is correct in that they are always in user mode. In these cases only the user mode definitions apply. The privilege mode definitions can be ignored if you are using the NMPU associated with one of the non-CPU bus masers.
  • 0 in reply to Chuck Davenport
    Intellectual 885 points

    Hi Chuck,

    I want to confirm with that what is the run mode of the bus masters in the Peripheral Interconnect Subsystem.

    The DMA, HTU1, HTU2, EMAC run in the user mode when access memory or registers?

    The DAP, DMM run in the privileged mode?

    What I have confrimed is that the DMA and EMAC run in the user mode, but I can not find any information about the mode of the others.

    Best regards,

       Eric

  • 0 in reply to Chuck Davenport
    Intellectual 885 points
    Hi Chuck,

    Any answer to my new question?

    Best regards,
    Eric
  • 0 in reply to eric
    TI__Guru 59540 points
    Hello Eric,

    My apologies for the late response but our support team is located in Houston, Tx which you may have seen has been severely impacted by Hurricane Harvey and subsequently severe flooding. We are only now starting to get back online and working to get back to normal support activities.

    I had forwarded this question to a colleague prior to our site being closed but had not yet heard back from him on it yet. My belief is that the DAP and DMM are not covered by an NMPU as they are predominantly debug related IP that are only used during development and potentially during manufacturing. Our safety manual gives the primary diagnostic to disable these features during application runtime as they are not considered as part of the safety operation of the device.

    I will continue to pursue a more definitive answer from our device expert, but I believe my statements to be accurate (90% confidence level).