• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 31 subscribers
  • Views 1193 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM42L432: RM42L432

Geng Yue
Intellectual 535 points
Part Number: RM42L432

Hi Everyone,

I am testing the MibSPI RAM parity. In our project, we use MibSPI to communicate with a peripheral. The MibSPI is working in multibuffer mode to transmit/receive data. After I initialize the MibSPI RAM, I want to test the parity and once I filpped a bit in the parity address, a data abort exception interrupt arrived. I checked the ESM register and there was no group 3 error occured. In my opinion, the MibSPI RAM parity can not be tested after the MibSPI RAM has been initialized, am I right? Or there are other opptions?

  • 0
    Expert 1995 points
    If you are running this function in a task, what priority and privilege settings are you using?
  • 0
    TI__Guru 59540 points
    Hello Geng,

    There is a PTSTEN bit within the register space that can be used to enable a Parity test mode. In this mode, you are able to update the RAM value without impacting the parity bits in the parity bit memory. Please see this post for more details and some example on how this is done: e2e.ti.com/.../150712
  • 0 in reply to Chuck Davenport
    Intellectual 535 points

    Hi Chuck，

    As you shared, I am using the same way as the post. But once I flapped the parity bit, a exception interrupt arrived!

    How can we slove this problem??

    Thanks!

    BR!

  • 0 in reply to Geng Yue
    TI__Guru 59540 points
    Hello Geng,

    As I mentioned in an earlier thread, my access to a test bench is limited at the moment so I can only make some observations and potential suggestions for this.

    First, are you running the device at 100MHz = HCLK = VCLK? If so, can you try halving the VCLK speed so VCLK = HCLK/2 and see if this impacts the success of the test?

    If so, can you again try to strategically place some NOPs in the code and try again at the full speed HCLK = VCLK? Specifically, place 2 NOPs after enabling the PAR test mode bit? Again, this may be a timing related issue at full speed where there is a need for some delay after enabling the test mode in order for that bit to propagate through to the register.

    This is really just some speculation on my part so it may not be the root cause. I will do some additional testing when I am able to return to the office next Tuesday, Sept. 5th.
  • 0 in reply to Chuck Davenport
    Intellectual 535 points

    Hi Chuck,

    Thank you for the reply! I heard the disaster in your country! Please take care! I will test as you memtioned above!

    Best Regards!