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NHET Parity RAM write access by CPU when TEST Bit is set and PARITY_ENA=0x05 or 0x0A

Pashan
Intellectual 715 points

 Hello,

Please answer below each question separately.

1> Is it possible to write 1-Bit data or 32-Bit Data to Parity RAM Area of NHET from CPU side when the HETPCR Register have TEST Bit set and PARITY_ENA=0x05?

2> Is it possible to write 1-Bit data or 32-Bit Data to Parity RAM Area of NHET from CPU side when the HETPCR Register have TEST Bit set and PARITY_ENA=0x0A?

3> Does HETGCR  HET_ON Bit control in any way write access to NHET Parity RAM Area from CPU when TEST Bit of HETPCR is active?

Assume PENA bit is set so that NHET Peripheral is visible to CPU and active.

Thank you.

Regards

Pashan