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RM57L843: ESM Group 2 Channel 3 triggered right after __TI_auto_init()

canfoderiskii
Expert 2255 points
Part Number: RM57L843
Other Parts Discussed in Thread: LAUNCHXL2-RM57L, HALCOGEN

Some background information and Problem Details:

  • Hardware Platform: LAUNCHXL2-RM57L
  • HALCoGen:4.06.01.
  • Problem: Every time the processor finished executing __TI_auto_init(), the register ESMSR2 is changed to 0x8. This problem can be reproduced 100% on my hardware platform.
  • checked this topic already: . But I don't have the same situation here: I don't use EMIF at all.
  • In the CCS Debug Configuration, I selected ECC generation.

Some testing results:

  • I used the startup code generated by HALCoGen, in which _memInit_() is called.
  • I tested with MPU enabled or not enabled. In both cases will the problem occur. So it should not be a MPU problem.
  • I checked some addresses of SRAM  in Memory View, and their values are all Zeros. Besides, the value of  RAMERRSTATUS in L2RAMW is 0(via Register View). So I guess the SRAM is running good.
  • I tried to enable the PMU and its event counters to count these 3 events:
    • Event Ref 0x6f - All fatal events
    • Event Ref 0x70 - All correctable bus faults
    • Event Ref 0x71 - All fatal bus faults
    • Found that right after __TI_auto_init(), those 3 counters' values are 1/2/1 respectively.
  • Sometimes I let the CPU run freely for some time(The main program does these:  tuning on/off LED using GPIO, reading value from RTI free-running counter and reading PMU event counter), I found that the 3 counters values are all incremented, changed to 3/5/3 respectively in one test.

Question:

  1. How does this problem happen? and how to solve it?
  2. I guess the probability of fatal events and even the correctable events counted by the PMU event counters is a little too high. Should all of them are 0 in normal situation?

  • 0 in reply to canfoderiskii
    TI__Guru 59540 points
    Hello Canfoderiskii,

    I apologize for the delay in getting back with you on your post. We have been in the process of ramping back up after being virtually off line due to the affects of Hurricane Harvey. I appreciate your patience as we attempt to take care of the support backlog.
  • 0 in reply to Chuck Davenport
    Expert 2255 points

    It's okay, there is no need to apologize, as Hurricane Harvey is horrible.

    I haven't looked into this problem for some time, is there any suggestion now?

  • 0 in reply to canfoderiskii
    TI__Guru 72500 points

    On this device ECC is always enabled. If you have properly initialized the SRAM, then the issue might be that you are getting an ECC error from the flash when you enable the cache. Each cache line loads 32 bytes from flash. Sometimes the section does not end on a 32 byte boundary and the ECC may not be generated for the missing bytes. That can be fixed by changing the align keyword in the sections part of the link command file with a palign (which means to pad and align). To avoid HALCoGen overwriting the change to my HL_sys_link.cmd file, I use #if/#endif as shown below:

    /*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
/* USER CODE BEGIN (5) */
    .intvecs : {} > VECTORS
    .text   palign(32) : {} > FLASH0
    .const  palign(32) : {} > FLASH0
    .cinit  palign(32) : {} > FLASH0
    .pinit  palign(32) : {} > FLASH0
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
#if 0
/* USER CODE END */
    .intvecs : {} > VECTORS
    .text   align(32) : {} > FLASH0 | FLASH1
    .const  align(32) : {} > FLASH0 | FLASH1
    .cinit  align(32) : {} > FLASH0 | FLASH1
    .pinit  align(32) : {} > FLASH0 | FLASH1
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
	

/* USER CODE BEGIN (6) */
#endif
/* USER CODE END */
}

  • 0 in reply to Bob Crosby
    Expert 2255 points
    Thank you so much. I tried and it works!