DK-TM4C129X: Serial Memory MX66L51235F Quad access qssi

Hi,

I try to develop driver for Serial Memory (MX66L51235F) .... for this purpose i refer to sample codes in www.ti.com/.../TIDM-TM4C129SDRAMNVM.... ""ektm4c129_qssi_example""...

I am ample to perform read/erase/write in spi mode...Now i have to use the quad read mode... for this after referring to sample code I tried following code snippet


/**********************************///*************************//
//*************************//
SSILibSendReadDataAdvBiQuad(SSI3_BASE,0x0,INS_QUAD_READ_DATA);// configure for Quad read mode



for(uint32_Index=0;uint32_Index<NUM_SSI_DATA-1;uint32_Index++)
{
SSIDataPut(SSI3_BASE,DUMMY_BYTE); // Dummy cycle
SSIDataGet(SSI3_BASE,&pui32DataRx[uint32_Index]);//read
}
SSIAdvDataPutFrameEnd(SSI3_BASE,DUMMY_BYTE); // end frame
SSIDataGet(SSI3_BASE,&pui32DataRx[NUM_SSI_DATA-1]);

for(uint32_Index=0;uint32_Index<NUM_SSI_DATA;uint32_Index++)
{

UARTprintf("Mem loc %d with value as %x\n",uint32_Index, pui32DataRx[uint32_Index]);

}



Though the uC configured for QSSI (observed on scope) access ,the memory chipset doesnot respond to the Quad read cycles.....In ""MX66L51235F"" data sheet Pg 46 under title ""Quad Read Mode (QREAD)""

""A Quad Enable (QE) bit of status
Register must be set to "1" before sending the QREAD instruction.""


Where as in the function

SSILibSendReadDataAdvBiQuad();


Quad Enable QE bit in status register is set to "zero" before the QREAD command is issued...


is it correct pls confirm...


Do you have any sample codes to handle SSI serial memory interface??

Hello Rakesh,

I am not familiar with this example nor Quad mode for SSI, so I may be missing the pertinent line, but right now my review of the code doesn't indicate to me there the Quad Enable bit in the status register is being set to zero, can you clarify this?

Also the code by default should include QSSI reads, can you try running it without modifications to see if that works?