Clock Source Disable register setting for Clock Source 0 and Peripheral Asynchronous Clock Source relation

Pashan,

The central clock controller module manages the mapping of the available clock sources to the clock domains on the microcontroller. The clock controller also ensures that a clock source is not disabled while it is being used by an active clock domain. The below sequence needs to be followed in order to disable a selected clock source.

• Set the correct bit in the CSDIS register, or write to the CSDISSET register with the appropriate bit set (preferred method)
  • The clock control module will not allow the selected clock source to be actually disabled until there are no clock domains actively using this source. In your case, the DCAN module AVCLK1 domain is using the main oscillator, which prevents the oscillator from being disabled.
  • This is an important safety mechanism implemented on the TMS570 microcontrollers.
• Set the correct bit in the CDDIS register, or write to the CDDISSET register with the appropriate bit set (preferred) to disable the clock domains not required
  • In your example, you can disable the AVCLK1 domain. Again, the clock controller module will actually gate off the AVCLK1 clock domain only when the DCAN module "reports" that it is no longer using this clock domain. So you can imagine that when the DCAN module is communicating on the CAN bus, it will not allow the AVCLK1 to be turned off.
  • This is another important safety mechanism implemented on the TMS570 microcontrollers.
• You can choose to wait for the DCAN module to allow the AVCLK1 to be turned off. Once AVCLK1 is turned off, the source used for this clock domain can be turned off if no other clock domain is also using  this clock source. Note that the PLL being enabled also counts as the main oscillator being used.
• Alternatively, you can select another clock source for the AVCLK1 domain, say the HF LPO (clock source #5). Then the main oscillator can be disabled (again, if no other domain is using it as source).

Hope this explains the dependencies between the clock sources and clock domains better. Let me know.

Regards,

Sunil

Pashan,

The high-frequency output of the LPO is chiefly used for monitoring the main oscillator. The clock monitor detects an oscillator failure of the main oscillator frequency falls outside of the 1.5MHz to 50MHz frequency range. These are the extreme ends of the range. The actual range could be smaller.

When you disable the HF LPO via the CSDIS register, the clock monitoring does not automatically get disabled. This causes the clock monitor to signal an oscillator failure. Moreover, the clock domains sourced by the main oscillator are switched over to the HF LPO, which is now disabled.

This causes the device to hang if the CPU clock domain is sourced by the main oscillator. This is the default case.

Suggestions:

1. Leave the LPO clocks running, as they provide the important oscillator monitoring capability
2. If you do need to disable the LPO clocks, then first disable the clock monitoring via the CLKTEST egister at address 0xFFFFFF8C.
   • Set the RANGE DET ENA SSEL bit (bit # 24) and leave the RANGE DET CTRL bit (bit # 25) as 0.
3. Now the clock monitoring can be enabled/disabled under software control, with it being disabled by CLKTEST register bit 25 (RANGE DET CTRL = 0).
4. If no clock monitoring is required, you can turn off the LPO at this time via the CSDIS register.

Regards,

Sunil