TM4C1294NCPDT: GPIO direct driving digital switches 24 volts

BP101 said:

Curious if anyone thinks it dangerous to drive a digital PNP switching 24 volts via GPIO output required to drive a relay?

I would use the phrase stupidly parsimonious.

A SS-FET not going to cost much more than a schottky, it might even be less. And really that 2N3906 should be replaced with a FET as well.

Robert

You could have the GPIO drive a small NPN xstr (rated to 30V) and the (open collector) of the NPN (which is pulled up) drives the gate of a small PFET.    (PFET gate is thus switched from 24V to (near) 0V - turns ON when its gate is driven (near) 0V.)      BTW - you write of "GPIO" - yet we cannot "find" such GPIO w/in your schematic.    (assumed from "Mims Jr.")

The NPN is operated as a simple inverter - perhaps 1K series base R - emitter tied to ground.

The use of the "555" is curious - cannot the MCU provide such "timed functionality?"      (and freed from "R-C" value drift/aging, voltage variation & ALL of those components...)

Robert Adsett72 said:

A SS-FET not going to cost much more than a Schottky, it might even be less. And really that 2N3906 should be replaced with a FET as well.

The Tina simulation 2n3906 is mimicking intended digital PNP, assume acts much like a digital FET that a GPIO 3v3 direct drives the gate, PNP base. The control of the PNP switch is not well documented as it relates to digital levels, same goes for the digital FET's I've worked with. CB1 mentions use open collector NPN, such may act like Schottky diode protect GPIO port from 24v potential. The point is the digital PNP switch has E to B voltage limitations, especially when SD1 was not installed with R3 5-10k ohms.

The other innate problem with using digital FET switch to drive digital PNP is the threshold of the N channel FET is very low (850mv typ.) difficult to control the PNP base below 1v to gain 500mv-23.79v at RL1. The reason for selecting digital PNP with 500ma drive over selecting digital FET acting alone is a 25Bvd 200ma N channel. The PNP switch will likely never short out from spikes ESD or other coil related miss jiff and is cheep 0.24cent. Alternatively a 5v Panasonic relay sinks 187ma, a 24v relay 38ma      huge difference when a single 5v 500ma buck down is supplying two 3v3 LDO's already.  

Notice the Tina simulation TLC555 VCC is set to 3v3 as to simulate the GPTM CCP output.

cb1_mobile said:

"Why employ the arcing/spiking/current-hogging/ESD generating" RELAY when the PFET (already suggested) can easily (And cleanly) switch several Amps (or more)?

One would think that an easy remedy for FET yet TI tutorial TPS22969 (load switch) suggests an PFET may falsely drive on POR. TI load switch rated 5v @6amps blocks POR false drive, perhaps good for a 5v relay driver yet not enough voltage to drive an FET gate into full conduction where RDS is greatly reduced.

cb1_mobile said:

Imposing the small NPN between MCU & PFET does not act like a Schottky - it properly provides "switched gate drive" to the PFET -

Actually required a PNP in Tina as TCL555 sets immediately on POR for 1.5 seconds then out pin 3 goes low, avoids pitfall of PFET false conduction on POR occurring. Notice the AM1 graph line starts at 8 amps based on the PTC provided in Tina yet if the relay contacts were to close suddenly on POR the current spikes near 60 amps again based on Tina PTC model. 

https://training.ti.com/load-switches-vs-discrete-mosfets

A PFET - with its gate properly pulled up/filtered - is unlikely to "falsely conduct" during Power On.    (there are known (standard) methods to prevent such)

PFETs avoid the requirement of gate drive ≥5V. (wrt Gnd)     The imposed, open-collector NPN, (between MCU & PFET) provides the PFET's gate drive when its base is turned on.   (pulling the PFET's gate to (near) Gnd - switching it On.)

Might your past methods have caused your (as poster Robert notes) likely unnecessary, "Premature Optimization?"

Surely your study of the "Mim's Jr. booklet" revealed the damning effects of "RELAY CHATTER" - far more destructive than (most unlikely) PFET glitch...

cb1_mobile said:

PFETs avoid the requirement of gate drive ≥5V. (wrt Gnd)     The imposed, open-collector NPN, (between MCU & PFET) provides the PFET's gate drive when its base is turned on.   (pulling the PFET's gate to (near) Gnd - switching it On.)

Might try to simulate PFET being C3,C4 is only 1720uf versus 13200uf of the soft start relay circuit. Ti training video link shows the PFET drawn as NCHAN device the gate driven by PCHAN. Yet states several bad things can occur, is that a N channel inline or what? One thing to consider AM1 only shows the reverse current in Tina and the forward current through C3,C4 is unknown when the load is sourcing 45 amps from supply.

Check around time line 6:53:

https://training.ti.com/how-and-why-replace-discrete-mosfets-load-switches

Yep training video has FET channel arrows reversed on both PMOS & NMOS, really confusing the entire presentation. The anomaly being mentioned @10:54 is a deal breaker, seemingly a PTC placed across the PMOS might arrest the surge.

https://training.ti.com/how-and-why-replace-discrete-mosfets-load-switches

I would add as (both) Robert & I noted (here) yesterday - you have "steered your solution" to a (likely) "less than stellar port!"     (a proper forum would, "Restate & Award a LIKE" for working "stellar/Stellaris" (RIP) in!)

Why was the bipolar PNP chosen as switching device?      

If you seek to,

• "Switch to Gnd." then a logic-level NFET makes far more sense - reduces BOM - and is more robust.
• "Switch to 24V"  then a "NPN or NFET" driving a PFET - (described multiple times, earlier) makes most sense.

Your opening post "questions" the safety of your PNP choice - rightly so - your REAL quest should be PNP's elimination.    (NOT adding lip-gloss to (another) pig...)

cb1_mobile said:

 Use of an NFET to "Source such voltage" demands that the NFET's gate be driven (~10V higher than the voltage you seek to switch) - requiring an added supply or charge pump or (most likely) gate driver IC.

Interesting though not entirely true as too discovered Robert was thinking similar and Tina confirmed true below.  NFET with 3.8v gate threshold on low side conducts well before 10v though what of the dissipation QGD etc.. The pro is 24v relay can be entirely removed (cost savings) the con as TI load training eluded to is capacitive pre-charge seems to occur through DS prior to 162v being switched, e.g. 2ohm IPC.

cb1_mobile said:

You may impose a simple NPN or small NFET (say 2N7002) - (as previously stated, between the MCU and PFET.)    Such NPN or NFET inverts the MCU's GPIO output - provides NO path for 24V (back to the Micro) and thus (safely) switches the PFET's gate between 24V (when OFF) and (near) Gnd. (when ON).

Tested open collector NPN but could not achieve a 3v gate threshold for PFET or NFET, the digital PNP seems best to switch 3v3 supply to the FET gate,  switching +5v to +15v for some reason FET gate threshold will not react as you would think it might.  Edit: The current via R10 was well above GPIO 12ma rules out direct switching NFET even via pre-biased BJT digital PNP.

More over 162v was pre-applied earlier Tina simulation/graphs yet when 5ms less/more delay (VG2) is inserted, a 58 amp capacitive pre-charge spike occurs via proper rated ICL stated to arrest such capacitive pre-charge surge. Currently soft start HVDC supply has 330 ohm 10 watt parallel shorting switch (manual) series 162v and 1.5 second POR delay 2.5kw supply for low/high voltage DC. So consideration for TM4C1294NCPDT being impacted by unforeseen POR spike Tina simulations (Relay/NFET) as each circuit produces a 58 amp POR spike in the HV +/-5ms delay.

BP101 said:

  {here quoting cb1}

Use of an NFET to "Source such voltage" demands that the NFET's gate be driven (~10V higher than the voltage you seek to switch) - requiring an added supply or charge pump or (most likely) gate driver IC.

{and below is BP's response}

Interesting though not entirely true  

The ~10V (V_gate over V_Drain) is for a "standard" NFET - "logic level" devices may work w/lesser voltages - yet their specs reveal they are (most) always "compromised" as compared to standard NFETs - or when driven at higher V_gate levels.   (so long as V_gate spec is honored.)

From a decision-maker's perspective - you've enabled a firm, "Not Famed" for Power FET expertise - to cast doubt upon Power FETs.     Would not your review of the (far more appropriate) resources of (real) FET makers (Infineon - swallower of IR) prove much more appropriate?     (Ans: mais oui - certainement!)     Somehow - thru the "fog of battle" - you appear to have missed that truth!

Good luck w/your project (whatever it is) its a bit too "weedy" now for my taste and (without doubt) an NPN/NFET - driving a PFET - is a classic technique to Source Voltage & various current levels.    And w/proper design avoids the POR issue - IR & Infineon's App Notes/Tech expertise prove far superior - in this (FET) regard.

For those interested in further "P-FET as High-Side Switch" circuit details - the following link is provided:
www.onsemi.com/.../AND9093-D.PDF     (there are other, similar write-ups, as well)

This is a relatively simple, 7 page (fast read) which well illustrates the use of a "P-FET" as the "Pass Element" when one seeks to achieve, "High-Side Switch Control."     In particular - Figs. 5, 6 & 7 refute the (vague & unsubstantiated claim) of "bad things" resulting.

Proper designs are (most often) properly successful...

BP101 said:

cb1_mobile

 Use of an NFET to "Source such voltage" demands that the NFET's gate be driven (~10V higher than the voltage you seek to switch) - requiring an added supply or charge pump or (most likely) gate driver IC.

Interesting though not entirely true as too discovered

Yes, it's pretty much entirely true.

BP101 said:

The pro is 24v relay can be entirely removed (cost savings) the con as TI load training eluded to is capacitive pre-charge seems to occur through DS prior to 162v being switched, e.g. 2ohm IPC.

You're still switching on the high side, why are you switching on the high side? It serves absolutely no purpose. Similarly the 100k paralleled across the FET.

Your gate resistor is entirely too large, that PTC shouldn't be there, neither should those caps. Probably a pull-up or pull-down to reflect the default state. Have you even looked at standard gate drive circuits?

Also, as near as I can tell your FET doesn't exist anymore. It appears to be quite ancient in MOSFET terms (with a large off state current). A better choice given that load (24V/8ma) would be a standard SS FET like a BSS123 (reduces the off-state current by three orders of magnitude, and is readily available from multiple suppliers).

Robert

Robert A.: "Why not use germanium point diodes while you're at it?"    Clearly - "Tag of the Month" - SO much more insightful than retarded TM4Cxyz!"

Poster Brett has an affinity for (the departed) Radio Shack's Tech Lib.   (even though I've steered him towards "Robert's Bookshelf") and such "hobby-based circuits" ARE "Bit long in the tooth."

Of course the danger in copying such passé circuits - often the devices were sub-standard/fall-outs - and (even when performing (barely) to spec) - cannot compete w/those issued today.

You are of course correct to question Brett's choice of "Hi-Side" switching - especially as this complicates the design - and "no identifiable benefit" has been identified!    (yet again - when "helpers" BOW to poster's "method of attack" - can such inefficiencies (really) be avoided?     (Ans: Hell NO!)

Further - while never explained - it is (likely) that the requirement for 24V sprang from the, "Use of a Relay!"    (which it is assumed - goes (nicely) w/germanium point diodes...)

Posters would fare far better if they presented, "THEIR OBJECTIVE" - UNENCUMBERED BY THEIR "SOLUTION!"

May a "LIKE-less" and "LABOR-less" day be enjoyed by all.    (those w/in the USA/possesions)

What in the world are you two clamoring about ?? high side FET switching is not illustrate in any schematic I posted.

@ Robert The ICL (250/500 ohm 40amp) is required to slow down reverse/forward inrush current into (empty) parallel 680uf capacitors, (1360uf)  instantly subjected to 163vdc directly reflects battery SOC. Otherwise when no ICL a huge 200-1k amp or more current spike occurs before the FET (ever) switches on (same for NO relay contacts). The FET is switched on only after a soft start delay cycle, roughly 90v-130v as a LOW side switch to ground (no CP) directly required. A digital PNP can source almost full 3v3 supply @500ma to the FET gate as it adds electrons. The gate pull down R2 can be between 10k-100k in this low threshold bias mode.

The part you two missed is the TPS22969 is NFET load switch (not a PFET)  should work equally as well in PTC FET circuit --- once pre-charge and turn on soft start delay inrush spikes are removed from equation.. Both are arrested in simulation now after tweaking adding the actual vendor Spice macros. 

Like I stated once before an open collector NPN switch could not produce a high enough voltage (threshold) at the FET gate to even turn it on with 3v3 supply. Both LC555 and NFET bias are at the same voltage potential, this eliminates the need for SD1 that 24v relay circuit required.

I'm game to test any schematic either you present in Tina layout (*.TSC) and post the graph report.

Progress counts, Tina rings out transient bugs one by one. VM3= IRF540 NFET gate threshold, AM3= ICL current, AM1=inrush current.

Relay part is a proven circuit yet driving 2n2222 switching +24v direct from GPIO seems a bit risky after Tina shows higher than VDD potential on the transistor base resistor.  Basically the same issue with such huge reverse polarity, 1 diode drop why put a PFET drop in there too. Good thing is only the caps ground return path is via a FET in Tina, not the bridge drivers direct ground path makes far less of deal breaker..

ON Semi PDF also mentions use of NFET having less RDS then a PFET, makes me all rosy inside. Notice in Tina NFET source at ground versus the load and drain faces the load when at ground level just like another bridge driver near by. Happy labor day - I did all day long!

BP101 said:

What in the world are you two clamoring about ?? high side FET switching is not illustrate in any schematic I posted.

I'm afraid we (or at least I) misread your schematic. That's your gate drive up there at the top? I strongly suggest you get a copy of the Art of Electronics and read their section on drawing schematics. What you've drawn is opaque.

Let me re-emphasis our point. Get a proper gate drive circuit. The gate resistor is too high and even where you measure it the drive voltage is never high enough nor low enough. You're practically always in the linear region. That's a very bad thing.

BP101 said:

Robert The ICL (250/500 ohm 40amp) is required to slow down reverse/forward inrush current into (empty) parallel 680uf capacitors, (1360uf)  instantly subjected to 163vdc directly reflects battery SOC.

If you are concerned about inrush raising the bulk capacitors ground is likely to cause more problems than it solves. The proper way to deal with that is via a pre-charge circuit. The form that takes depends on the application. It could be a separate relay, or it could be a dedicated input that bypasses the on switch.

It could even be ignored entirely, depending on the capacitors. It was fairly common on our EV controllers to do do. The batteries could more than handle it, so could the caps.

Worse your chosen FET won't survive that voltage.

BP101 said:

The part you two missed is the TPS22969 is NFET load switch

Easy to miss obviously, I still don't see it in the circuit. Did you miss that it's a 5V device?

Wait a minute, are you trying to build a pre-charge circuit?

Robert

BP101 said:

mentions use of NFET having less RDS then a PFET, makes me all rosy inside.

Indeed that is true - yet comes w/the cost of (much) added circuit complexity!     (as stated - now repeated - to "appease" the NFET you must drive its gate "higher in voltage" than the FET's supply voltage.)    

This forces extra size, cost, & complexity upon the design - which accounts for the PFET's usage in (many) high-side switching APPS.    In fact - if you read any of the cell/tablet "tear-downs" - it is (almost) universally true that ONLY PFETs are employed to Switch Power!     (and these seem to (studiously) avoid the (claimed) POR plague - do they not?)

Note too that the vendor's article clearly, "Votes for the PFET" when currents are single digit.   Your "take away" was unlikely to reflect the author's (or cb1's) intent...

BP101 said:

BP101 said:

Relay part is a proven circuit yet driving 2n2222 switching +24v direct from GPIO seems a bit risky after Tina shows higher than VDD potential on the transistor base resistor.  Basically the same issue with such huge reverse polarity, 1 diode drop why put a PFET drop in there too.

So let's see if I've got this clear. You are intending on replacing the relay above with a FET?

Mind you it is true you've only got  about 225uF of capacitor here. Presumably in an attempt to get away with lower voltage caps you are placing them in series. That is about 1/6 the capacitance of your earlier circuit. Almost wondering why you care about inrush.

BP101 said:

Good thing is only the caps ground return path is via a FET in Tina, not the bridge drivers direct ground path makes far less of deal breaker..

Say what!?Have you got a resistor isolating the two or something? And if this isn't across your bridge what is is across? And what is across the bridge? The capacitance across the bridge should be pretty substantial as well.

BP101 said:

ON Semi PDF also mentions use of NFET having less RDS then a PFET,

Sort of. That's true for a given set of constraints. RDSon isn't the sole figure of merit though.

Yes replace relay as CB1 eluded to several times but with NFET as you suggested, switching low side always intended. Capacitance remains 680uf maybe bit higher but no lower, series mode raises working voltage,    400vdc motor drive. Like to use TPS22969 perhaps parallel two gains 12 amps peak though afraid -0.3v max could easily be exceeded via Dv/Dt etc.. Training videos suggest to add only a cap to slope the load voltage ramp order soft start & arrest inrush, nice thing it direct drives via 3v3 GPIO port assume with little current drive. Was planning to use IR75 amp NFET not shown in these plots but perhaps that is an overkill. 

Robert Adsett72 said:

And if this isn't across your bridge what is is across? And what is across the bridge?

1360uf parallel caps shadow the bridge where the high side direct connects to (+ cap) and source ground via shunts from more robust copper path located several inches from caps. The circuit in this post provides a similar branching ground pathway, one for bridge high current, the other for capacitance ripple reduced current flow via PCB ground plane. The difference is the PCL cuts out when the really pulls in, if the relay fails the ICL must balance the entire load or take a punch and smoke but if the NFET DS did short no harm should ensue to HV. The ideal ICL will have a high start resistance to choke inrush and later reduce resistance under stain & constant current to keep the load running if the NFET fails. 

Robert Adsett72 said:

Sort of. That's true for a given set of constraints. RDSon isn't the sole figure of merit though.

SOA DC seems more of a concern NFET continuous IDS or QGD & being on ground side of capacitors gains isolation via many turns of foil/oil from ever seeing higher potentials near or above BVD, unless caps short out then main fuse blows.... 

BP101 said:

Yes replace relay as CB1 eluded to several times but with NFET as you suggested, switching low side always intended.

That doesn't make sense for this load. Too many things would be affected by raising the ground.

BP101 said:

Capacitance remains 680uf

No it does not, in either case.

in your first schematic you had two 680uF caps in parallel for (2x680)uF total, in your second you have three 680uF caps in series for (680/3)uF total (provided your caps are well matched).

BP101 said:

Like to use TPS22969 perhaps parallel two gains 12 amps peak though afraid -0.3v max could easily be exceeded via Dv/Dt etc..

That's a 5V device you cannot, simply cannot use that on a 163V bus.

BP101 said:

Robert Adsett72

And if this isn't across your bridge what is is across? And what is across the bridge?

1360uf parallel caps shadow the bridge where the high side direct connects to (+ cap) and source ground via shunts from more robust copper path located several inches from caps. T

Umm, so you are concerned about the current spike into ~230uF but the current spike into 1360uF is irrelevant?

BP101 said:

The circuit in this post provides a similar branching ground pathway, one for bridge high current, the other for capacitance ripple reduced current flow via PCB ground plane.

!!???

BP101 said:

SOA DC seems more of a concern NFET continuous IDS or QGD & being on ground side of capacitors gains isolation via many turns of foil/oil from ever seeing higher potentials near or above BVD, unless caps short out then main fuse blows.... 

I'm having trouble even parsing that.

Robert

Robert Adsett said:

in your second you have three 680uF caps in series for (680/3)uF total (provided your caps are well matched

Similar value capacitors in series only increase the working voltage, total capacitance will be no less than the smallest capacitor value, the same is true for working voltage. 

Robert Adsett said:

That doesn't make sense for this load. Too many things would be affected by raising the ground.

Ti engineer who developed ground bypass circuit didn't think that the case. The ICL thermal resistance and NFET's RDS react mostly to (capacitive ripple current) flowing to ground but not so much for the bridge current as C3 C4 mostly acts as a filter & B+ current source store not the actual voltage source per say. Not much reverse current is expected through or from C3 C4 ground as the bypass is not directly connect to the bridge ground source. E.G. Current flow (always) takes the least resistive path to ground, Ohms law perhaps is true.

Robert Adsett said:

Umm, so you are concerned about the current spike into ~230uF but the current spike into 1360uF is irrelevant?

Not sure how to parse that -- did you not review the attached Tina graphs less than 700ma results.

Robert Adsett said:

That's a 5V device you cannot, simply cannot use that on a 163V bus.

Check again where exactly is the NFET located ? not on the high side but right on ground same goes for TPS22969 hook up. That forum is checking it out.

BP101 said:

Robert Adsett

in your second you have three 680uF caps in series for (680/3)uF total (provided your caps are well matched

Similar value capacitors in series only increase the working voltage, total capacitance will be no less than the smallest capacitor value, the same is true for working voltage. 

No, no, no, no!

See for example http://farside.ph.utexas.edu/teaching/302l/lectures/node46.html I learned this in junior high and nothing has undermined that basic understanding since.

Robert

BP101 said:

Robert Adsett

Umm, so you are concerned about the current spike into ~230uF but the current spike into 1360uF is irrelevant?

Not sure how to parse that -- did you not review the attached Tina graphs less than 700ma results.

Yes, but you indicated that was for the same circuit you presented later with capacitors in series. So you are saying now you have two backs of capacitors with two different pre-charge circuits?

BP101 said:

Robert Adsett

That's a 5V device you cannot, simply cannot use that on a 163V bus.

Check again where exactly is the NFET located ? not on the high side but right on ground same goes for TPS22969 hook up. That forum is checking it out.

Riddle me this. With the FET off what's the maximum voltage across the FET when voltage is applied? This should be a simple back of the envelope calculation for you. Or you could just calculated from the simulation results you already have.

BP101 said:

Robert Adsett

That doesn't make sense for this load. Too many things would be affected by raising the ground.

Ti engineer who developed ground bypass circuit didn't think that the case.

Was it developed for this load with the FET bridge bypassed? I strongly suspect not.

BP101 said:

The ICL thermal resistance and NFET's RDS react mostly to (capacitive ripple current) flowing to ground but not so much for the bridge current as C3 C4 mostly acts as a filter & B+ current source store not the actual voltage source per say. Not much reverse current is expected through or from C3 C4 ground as the bypass is not directly connect to the bridge ground source. E.G. Current flow (always) takes the least resistive path to ground, Ohms law perhaps is true.

First that's an oversimplification, the current will flow along the path of least impedance, not resistance. The difference matters when dealing with high speed currents like you are. Second, where do you think the capacitor ripple comes from?

Robert

cb1_mobile said:

  (as stated - now repeated - to "appease" the NFET you must drive its gate "higher in voltage" than the FET's supply voltage.)    

Umm relative to this post the NFET is not powering a B+ rail, perhaps a PFET would not be as good a fit in a ground bypass circuit. No charge pump is required since the NFET source terminal connects to ground and only the gate source potential must only elevate to GS rated threshold since the drain never reaches close to BVDSS being so near to ground, seemingly there is only minimal RDS voltage drop. That brings into question the SOA table for continuous DC current below 50 or so amps falls to the far left of table below the last & bottom period line. 

On the other hand the PTC remains at high impedance unless rapid current change occurs across NFET DS, then it too reduces resistance value under thermal change from elevated current load.

 Yet the electrolytic capacitor is a DC device and innately separates ground from B+ so the bypass with NFET or even a PFET might just work equally well.

cb1_mobile said:

Note too that the vendor's article clearly, "Votes for the PFET" when currents are single digit.   Your "take away" was unlikely to reflect the author's (or cb1's) intent...

My take away was the PFET was intended for the B+ rail not the ground rail which seems to get over looked in power control systems since most are considered AC powered not DC battery. Might it be such low RDS values never past existed so many engineers assume inrush current is covered by an ICL in the AC power side of an DC inverter. Seemingly DC solar panel and HEV technology has evolved the need for engineers to get out of that moist seat and do some lab experiments in ground side power control..

https://www.onsemi.com/PowerSolutions/segment.do?segmentId=Automotive&utm_source=home-page-banner&utm_medium=hpb&utm_term=&utm_content=link-automotive-page&utm_campaign=automotive

BP101 said:

My take away was the PFET was intended for the B+ rail not the ground rail

Yes, and for obvious reasons involving shifting grounds in power circuits. It could be done but for low power systems a PFET on the high side will work as well and higher power systems would either not pre-charge or use a contactor.

BP101 said:

Seemingly DC solar panel and HEV technology has evolved the need for engineers to get out of that moist seat and do some lab experiments in ground side power control..

You have been talking about pre-charge, not control. Different problem area. EV's have been using low side power control since at least the late 80's while still pre-charging the high side (or not pre-charging)

Robert

BP101 said:

...has evolved the need for engineers to get out of that moist seat and do some lab experiments in ground side power control..

Said "moist seat" describes yours too - does it not?        Enough "free consulting" - the world (or at minimum this forum) - awaits the "next" BP "breakthrough!"

BTW - your subject line, "Direct driving a PNP Digital Switch" reveals your serious "design flaw" - that of "Direct Drive" from a (severely) limited "span voltage."   (MCU GPIO provides a 3V3 voltage span - as you know)    

My (first answering post's) suggestion "imposing an "NFET or NPN" between the MCU & (PNP or (preferred PFET)" would have enabled your "full & proper" control of your PNP (or PFET).     This proves true as the NFET or NPN enables a (near) 24V span to the PNP/PFET's (base or gate) input - enabling proper switching action...

The use of the relay remains curious - the PFET can reliably deliver the 24V which your Subject Line & Opening Post Schematic (via improperly driven PNP) sought...

Robert Adsett said:

Riddle me this. With the FET off what's the maximum voltage across the FET when voltage is applied? This should be a simple back of the envelope calculation for you. Or you could just calculated from the simulation results you already have

Notice graph last posted is a transient analysis of the reactive energy in the NFET circuit not the TI relay bypass similar to the one initially posted, accept the caps are parallel in Tina analysis and uses 2 digital PNP. 

Stated several posts ago there is a 35ms -125ms delay in the 162v (VG2) being switched on, how does VM4 react to a sudden voltage shock across empty C3,C4?

The PNP driven relay transient analysis in Tina with parallel caps is not to far from the NFET analysis results however both have 500 ohm lieu of ICL at this point.  Vendors Spice macro issue being looked at.

Transient analysis operation point of circuit with 35ms delay switch B+ VG2 DC bus power, notice relay VM3 has not pulled in yet.

Robert Adsett said:

Notice you didn't even approach answering the question. VM4 is not the voltage across the FET

Actually VM4 starts at 0v and explains the drop across the DS is at 0V but I will do an operational VM analysis on DS just for giggles.

BP101 said:

Ok you win that one

If you define "that" in extremely limited terms.       (That) win represents "tip of the iceberg" - tis you who are here seeking design guidance/consulting...)

cb1_mobile said:

(That) win represents "tip of the iceberg" - tis you who are here seeking design guidance/consulting...)

So you didn't learn anything from Tina analysis input? How does the NFET being more reliable than a relay not justify vendors to build a viable solution that the TM4C1294NCPDT can directly control via GPIO port such as TPS22969 to replace an outdated bypass relay. Notice even the digital 2 PNP circuit sources near 26.16ma floats the relay @22v not 0v, current is far above a single GPIO port ability. That single NPN switch the C2000 engineer used to drive the 24v relay is dangerous to the GPIO port..

Hard to believe the US went to the moon decades ago and is still held hostage under DC capacitive inrush current. Seems to me for the billions spent there should be intelligent capacitors by now that don't surge when empty and still provide basic filtering of ripple. 

Robert Adsett said:

I learned this in junior high and nothing has undermined that basic understanding since.

Find it very odd a Ti engineer put only 226uf caps in a 400vdc motor inverter circuit to reduce GTO dv/dt and provide on PCB electron storage reserve. My proto DC inverter has 470uf 162v is hardly enough to reduce undesired FET dv/dt and as I understand GTO's are often great dv/dt offenders.

cb1_mobile said:

You may also select 5V GPIO - config to "open drain" - and properly "pull-up the gate to 5V

Tina graph showed TLC555 output above 3v3 with +5v digital PNP base tied to GPIO, OD Tina simulation of GPIO port would be golden about now. Fairchild FL3100T low side 15v gate driver seems a good match for GPIO drive current restriction 12ma max.  Do agree Tina showing results applying less than 3v3 at gate is highly risky to assume a low RDS is even possible, if not asking for real world fallout all together. 

Robert Adsett said:

No, no, no, no!

Have to admit never have put 3 or even 2 caps in series in 40 years let alone measure them with DMM cap checker, only last 3 years acquired that little jewel .

You are correct about divided similar value capacitance, checked series 3*680 on DMM and to my surprise far less value than expected them to measure. Must be the working voltage of different rated caps was thinking about but definitely not to use product over the sum.

Wonder if TIDA-00195 TIDUA15A PWM motor drive made same mistake or if 240uf seems ample reserve at 300-400vdc, seems to small for 22KW DC inverter IGBT module at end of long twisted pairs.. Perhaps now glad I didn't jump into that fire so quickly.

BP101 said:

Hard to believe the US went to the moon decades ago and is still held hostage under DC capacitive inrush current. Seems to me for the billions spent there should be intelligent capacitors by now that don't surge when empty and still provide basic filtering of ripple. 

There are capacitors that can withstand the inrush. The issue is often the external circuitry such as fuses or contactors.

Robert

BP101 said:

Have to admit never have put 3 or even 2 caps in series in 40 years let alone measure them with DMM cap checker, only last 3 years acquired that little jewel .

Fairly simple derivation from capacitor definition (as shown in the link I supplied earlier) would show it. As would a simple conservation of energy calculation.

BP101 said:

seems to small for 22KW DC inverter IGBT module at end of long twisted pairs..

Which end? If it's cap twisted pair and then bridge, I doubt any capacitance is large enough.

If it's twisted pair then cap and bridge, the twisted pair is a secondary consideration (try twisting 00 cable), although wrapping the source cables around an iron core is not recommended (we did have a customer do that).

Robert

BP101 said:

 let alone measure them with DMM cap checker

Well, it's not that difficult to measure capacitance of an electrolytic (at least to first order). All you need is a resistor and a constant voltage. Several resistors if you are concerned about exceeding your source capabilities.

A constant current source would work as well.

Robert

Robert Adsett said:

Which end? If it's cap twisted pair and then bridge, I doubt any capacitance is large enough

Check again the TIDI link above is edited but to answer YRQSTN, the induction motor of all places from what it seems holds IGBT module far from the PCB caps & gate drivers.

Meant to infer intelligent moon caps could slow down inrush current by design from some kind of futuristic molecular oil dressing between foil turns that also reduces cap ESR when saturated.