WEBENCH®︎ Tools/TMS570LS1224: How many ADC channels can sample the external signal at same time?

Hello Wu,

The TMS570LS1224 has 24 pins dedicated to ADC inputs. 16 of these pins have redundant inputs to each of the 2 ADC cores allowing each of these cores to sample the same signal and preform the conversion very close to one another. There will be some SW latency since you will need to instantiate the conversion for each core in SW or run them in continuous mode. If running in continuous mode, there is no guarantee that the samples will be at the same exact time.

However, if you mean you want 3 channels with 3 separate sources/signals to convert at the same time, it would be done by using the group conversion capability of the ADC module. This, however, will not sample all three at the same time. Each will be sampled and converted in sequence according to how the ADC is setup.  This is because each core can only convert one signal at a time.

In regard to timing, it is dependent on several factors such as ADCCLK, sample time, external influences such as input impedance, etc. Below is a table from the Datasheet showing the specific minimum times for the ADC which are also dependent on whether it is in 10 or 12-bit mode of operation.

Hi Chuck,

Thanks for your reply!

Could you explain more for the item 'it would be done by using the group conversion capability of the ADC module' ?

In my undertand, TMS570LS1224 have two ADC core, so only two external signal can be sampled at the same time.

We will use 12bit mode, the minimum delay time between two ADC channel is 0.6us except the external circuit effect.

I don't know it is right or not?

Thanks!

Hello Wu,

In our ADC modules, we define three different groups. Each ADC channel can be assigned to one or more of these groups. The SW would then start a group conversion and the ADC channels assigned to that group would be converted/sampled based on the order specified in the configuration of the ADC. By default this would be done serially. i.e., ADINx, ADINx+1, ... ADINx+y. The gap between conversions would be based on the overall sample and conversion times which will be dependent on ADCCLK setting. The external circuit influence would need to be determined by you since the settling time of any voltage change would need to be accommodated in the configured sample time settings.

If you use one of the pins with ADC1 and ADC2 inputs bonded to the same pin, you can sample the signal at nearly the same time, but not the exact same time. This is because you will need to initiate the ADC Group conversion for each ADC independently. i.e., say you connected your signal to a pin that has ADC1 channel x and ADC2 channel y. In the configuration of ADC1 your would assign channel x to a group (ex. Group1) conversion, and in ADC2 you would assign channel y to a group in ADC2 (ex. Group1 for ADC2). To perform the sample and convert, you would have to imitate the conversion on ADC1 Group1 then on ADC2 Group1 (i.e., both groups and ADCs are independent). So, there will be a small SW lag between initiating the conversion on ADC1 and then on ADC2. The total time between the instantiation of the conversions will be dependent on the SW, CPU speed, and setup/hold time for the sample and conversion itself.

Hi Chuck,
I don't fully understand of the explaination.
From specification, the ADC module has two MibADCs and each MibADC supports three separate groupings.
Named like, MibADC1_G1 / MibADC1_G2 / MibADC1_G3 / MibADC2_G1 / MibADC2_G2 / MibADC2_G3
For example, we have three external signals s1/s2/s3.
How to connect is the best way to reduce the gap? What's the delay time between three external signals?
Thanks!