Other Parts Discussed in Thread: HALCOGEN
Hi!
In Halcogen, I've generated code for the PLL and noticed that errata SSWF021#35 workaround states:
Workaround(s) Switch all clock domains to a different source (such as oscillator) before switching the
PLL output clock divider from divide-by-1 to a larger divider; after the PLL divider has
been changed, revert to the PLL as clock source for those clock domains.
In halcogen system.c file, mapClocks() function, the clock sources are not switched from PLL before changing the clock divider. See highlighted lines below:
/* SourceId : SYSTEM_SourceId_005 */
/* DesignId : SYSTEM_DesignId_005 */
/* Requirements : HL_SR469 */
void mapClocks(void)
{
uint32 SYS_CSVSTAT, SYS_CSDIS;
/* USER CODE BEGIN (11) */
/* USER CODE END */
/** @b Initialize @b Clock @b Tree: */
/** - Disable / Enable clock domain */
systemREG1->CDDIS = (uint32)((uint32)0U << 4U ) /* AVCLK 1 OFF */
| (uint32)((uint32)1U << 5U ) /* AVCLK 2 OFF */
| (uint32)((uint32)1U << 8U ) /* VCLK3 OFF */
| (uint32)((uint32)0U << 9U ) /* VCLK4 OFF */
| (uint32)((uint32)1U << 10U) /* AVCLK 3 OFF */
| (uint32)((uint32)1U << 11U); /* AVCLK 4 OFF */
/* Work Around for Errata SYS#46:
*
* Errata Description:
* Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
* Workaround:
* Always check the CSDIS register to make sure the clock source is turned on and check
* the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
*/
/** - Wait for until clocks are locked */
SYS_CSVSTAT = systemREG1->CSVSTAT;
SYS_CSDIS = systemREG1->CSDIS;
while ((SYS_CSVSTAT & ((SYS_CSDIS ^ 0xFFU) & 0xFFU)) != ((SYS_CSDIS ^ 0xFFU) & 0xFFU))
{
SYS_CSVSTAT = systemREG1->CSVSTAT;
SYS_CSDIS = systemREG1->CSDIS;
} /* Wait */
/* USER CODE BEGIN (12) */
/* USER CODE END */
/** - Map device clock domains to desired sources and configure top-level dividers */
/** - All clock domains are working off the default clock sources until now */
/** - The below assignments can be easily modified using the HALCoGen GUI */
/** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
systemREG1->GHVSRC = (uint32)((uint32)SYS_OSC << 24U)
| (uint32)((uint32)SYS_OSC << 16U)
| (uint32)((uint32)SYS_PLL1 << 0U);
/** - Setup RTICLK1 and RTICLK2 clocks */
systemREG1->RCLKSRC = (uint32)((uint32)1U << 24U)
| (uint32)((uint32)SYS_VCLK << 16U)
| (uint32)((uint32)2U << 8U)
| (uint32)((uint32)SYS_VCLK << 0U);
/** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
systemREG1->VCLKASRC = (uint32)((uint32)SYS_VCLK << 8U)
| (uint32)((uint32)SYS_VCLK << 0U);
/** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
systemREG1->CLKCNTL = (systemREG1->CLKCNTL & 0xF0FFFFFFU)
| (uint32)((uint32)2U << 24U);
systemREG1->CLKCNTL = (systemREG1->CLKCNTL & 0xFFF0FFFFU)
| (uint32)((uint32)2U << 16U);
systemREG2->CLK2CNTL = (systemREG2->CLK2CNTL & 0xFFFFF0F0U)
| (uint32)((uint32)1U << 8U)
| (uint32)((uint32)2U << 0U);
systemREG2->VCLKACON1 = (uint32)((uint32)(1U - 1U) << 24U)
| (uint32)((uint32)0U << 20U)
| (uint32)((uint32)SYS_VCLK << 16U)
| (uint32)((uint32)(1U - 1U) << 8U)
| (uint32)((uint32)0U << 4U)
| (uint32)((uint32)SYS_VCLK << 0U);
/* USER CODE BEGIN (13) */
/* USER CODE END */
/* Now the PLLs are locked and the PLL outputs can be sped up */
/* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFFU) | (uint32)((uint32)(2U - 1U) << 24U);
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFFU) | (uint32)((uint32)(2U - 1U) << 24U);
/* Enable/Disable Frequency modulation */
systemREG1->PLLCTL2 |= 0x00000000U;
/* USER CODE BEGIN (14) */
/* USER CODE END */
}
Please clarify if this is correct.
Thanks!
