Hello,
we have external device containing FIFO on EMIF bus. Therefore we need to block (prevent) any possible access to this memory region including speculative prefetch. It could be done by MPU unit, when we mark this region as device with execute never flag. But we have some strange observations about it.
Below there is part of Table 6-20 from datasheet SPNS162C. It describes, that needed region size for MPU unit is 16MB, and we understand, that remaining "reserved" space access are blocked. Of course without generation abort because it is speculative access, and this don't generate error.
Problem is that we observe rare but real access into this region with this settings. Almost same setting with 64MB region size works without problem.
From this observation we made conclusion, that address decoder for EMIF CS2-CS4 signals is incomplete and speculative instruction read can access to "reserved" addresses (for ex 0x63FF0000) and this generates real read cycle on bus. Is it correct?
For us, creating MPU setting for complete 64MB range solves this problem. But it needs confirmation from your side.
Jiri Dobry
