TMS570LS1224: Generate a corrupt RAM region

If you want to check for proper operation of the RAM ECC and you use HALCoGen to create your startup code, just select the "Enable ESRAM ECC Check" box.

This causes the function checkRAMECC() to be called in the startup after the RAM initialization.

/** @fn void checkRAMECC(void)
*   @brief Check TCRAM ECC error detection logic.
*
*   This function checks TCRAM ECC error detection logic.
*/
/* SourceId : SELFTEST_SourceId_034 */
/* DesignId : SELFTEST_DesignId_019 */
/* Requirements : HL_SR408 */
void checkRAMECC(void)
{
    volatile uint64 ramread = 0U;
	volatile uint32 regread = 0U;
	uint32 tcram1ErrStat, tcram2ErrStat = 0U;
	
    uint64 tcramA1_bk = tcramA1bit;
    uint64 tcramB1_bk = tcramB1bit;
    uint64 tcramA2_bk = tcramA2bit;
    uint64 tcramB2_bk = tcramB2bit;

    /* Clear RAMOCUUR before setting RAMTHRESHOLD register */
    tcram1REG->RAMOCCUR = 0U;
    tcram2REG->RAMOCCUR = 0U;

    /* Set Single-bit Error Threshold Count as 1 */
    tcram1REG->RAMTHRESHOLD = 1U;
    tcram2REG->RAMTHRESHOLD = 1U;

    /* Enable single bit error generation */
    tcram1REG->RAMINTCTRL = 1U;
    tcram2REG->RAMINTCTRL = 1U;

    /* Enable writes to ECC RAM, enable ECC error response */
    tcram1REG->RAMCTRL = 0x0005010AU;
    tcram2REG->RAMCTRL = 0x0005010AU;

    /* Force a single bit error in both the banks */
    _coreDisableRamEcc_();
    tcramA1bitError ^= 1U;
    tcramB1bitError ^= 1U;
    _coreEnableRamEcc_();

    /* Read the corrupted data to generate single bit error */
    ramread = tcramA1bit;
    ramread = tcramB1bit;

	/* Check for error status */
	tcram1ErrStat = tcram1REG->RAMERRSTATUS & 0x1U;
	tcram2ErrStat = tcram2REG->RAMERRSTATUS & 0x1U;
	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
	/*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
    if((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U))
    {
        /* TCRAM module does not reflect 1-bit error reported by CPU */
        selftestFailNotification(CHECKRAMECC_FAIL1);
    }
    else
    {
        if((esmREG->SR1[0U] & 0x14000000U) != 0x14000000U)
        {
            /* TCRAM 1-bit error not flagged in ESM */
            selftestFailNotification(CHECKRAMECC_FAIL2);
        }
        else
        {
            /* Clear single bit error flag in TCRAM module */
            tcram1REG->RAMERRSTATUS = 0x1U;
            tcram2REG->RAMERRSTATUS = 0x1U;

            /* Clear ESM status */
            esmREG->SR1[0U] = 0x14000000U;
        }
    }

    /* Force a double bit error in both the banks */
    _coreDisableRamEcc_();
    tcramA2bitError ^= 3U;
    tcramB2bitError ^= 3U;
    _coreEnableRamEcc_();

    /* Read the corrupted data to generate double bit error */
    ramread = tcramA2bit;
    ramread = tcramB2bit;

    regread = tcram1REG->RAMUERRADDR;
    regread = tcram2REG->RAMUERRADDR;

    /* disable writes to ECC RAM */
    tcram1REG->RAMCTRL = 0x0005000AU;
    tcram2REG->RAMCTRL = 0x0005000AU;

    /* Compute correct ECC */
    tcramA1bit = tcramA1_bk;
    tcramB1bit = tcramB1_bk;
    tcramA2bit = tcramA2_bk;
    tcramB2bit = tcramB2_bk;
}