Other Parts Discussed in Thread: HALCOGEN
Hello all,
We have a SPI 3 wires link in a board between MibSPI1 as master and MibSPI3 as slave.
Send is composed of 6x16 bits packets from TransferGroup0 and receive on TransferGroup0 too.
The behavior is the following :
- We have observed on oscilloscope clock and SIMO all is fine (when we are using compatible SPI3 we receive correctly all data)
- With MibSPI3 slave, only 5 first packets are present in Multi-Buffer RAM (as you can see bellow.
- We can see the sixth packet in mibspiREG3->BUF
- Nothing else receive from this point
You can found our project attached with halCogen.
1/ can you explain why the last packet is missing in the RAM buffer, while the data is in the BUF register?
2/ and why any next data from this point is not received?
Thanks for your help,
Best regards,
Alain,
