TM4C1294NCPDT: Is it possible to connect External ADC with TM4C1294 LaunchPad

What do you think?     Is your answer - rather clearly - not gleaned (first) from the "specs & interface requirements" of such (external) ADCs?

Then - reviewing the MCU specs - seeking an interface "match."     (such is highly likely)

You've made the effort to identify such ADCs - have you not?    Comparison between (their) interface (and timing) requirements - and your chosen (or modified choice) MCU - presents a solid answer...

Note that "some" poster effort IS required.    Board layout - especially when/where high-speed analog signals are present - demands care, insight, attention to (great) detail and "effort!"

I think it is possible.
Tiva board supports max. 60MHz SPI clock.
But I don't know how to decide which ADC to choose.

Thank you - your (so quick) response arrived as I was (still) composing my post. (refining)

SPI does appear to be your safest & best choice - this vendor and ADI (Analog Devices, Inc - having recently "swallowed" Linear Tech.) are assumed to be your, "best bet."

Both should provide "comparative ADC data - in user-friendly, tabular & limited parameter form - for your (eased) review."      You "key" upon the presence of the SPI interface - I do not believe that any (minimum) SPI clock rate is enforced - thus your chosen MCU should prove ok. 

Again - an ADC EVAL BOARD is mandatory - your construction attempts - unless highly practiced/skilled (and fortunate) - are (unlikely) to succeed...   (Not to ask - HOW I know!)

Krishnat Pawar said:

I think it is possible.
Tiva board supports max. 60MHz SPI clock.

Ummm....   Ah.... Umm....

Might I suggest a few sanity checks before you start?

• Do you need continuous or burst?
• How many SPI clocks do you have for each sample?
  • Is that enough?
• How many instructions do you have per sample?
  • Is that enough?

Finally don't forget to consider the challenge of transferring a 60MHz signal (with timing requirements in at least 120MHz region) across boards. This is an RF problem.

Robert

cb1_mobile said:

I would doubt poster has such "detail" - at the ready.

I think the only important information not presented is

• continuous or burst
• the amount of processing needed

The first should be answerable and at least order of magnitude of needed effort should be available.

Since we know the sample rate we can calculate the number of SPI bits available per sample. This will likely constrain the devices that can be considered substantially. Likewise we can calculate the clocks available per sample which will limit how much we can do for each sample during the time the A/D is active.

Given the information presently available SPI would not be my first choice.

Robert

Robert Adsett said:

Given the information presently available SPI would not be my first choice.

As - to my mind - SPI is fastest, most convenient serial data exchange format - are you thinking of "parallel?"

I note that some of these "fast acquiring ADCs" reduce their resolution (impacting their dynamic range - as you often note) (and teach).

cb1_mobile said:

As - to my mind - SPI is fastest, most convenient serial data exchange format - are you thinking of "parallel?"

That does reduce the frequency content of the signals to below the GHz range which simplifies layout. And for burst sampling I'd strongly consider FIFOs. For continuous sampling I'd want to take a real close look at the processing requirements, I'm not sure this would be the right processor.

cb1_mobile said:

I note that some of these "fast acquiring ADCs" reduce their resolution (impacting their dynamic range - as you often note) (and teach).

Yep

Robert

There is a high speed serial interface available for A/Ds called JESD204B. I've not used it and it's several classes beyond this processor I think.

Charles Tsai said:

Will this one work for you?

On a quick skim 25ns minimum conversion/chip select off time between conversions plus 9.5ns before the first clock edge leaves 165.5 nS to clock data or 9.9 SPI clock cycles to clock the data in.

If you can safely interrupt a read part way through and you can control the clocking that tightly then you may be able to get 9 bits per sample clocked out at maximum speed.

Robert

There's a reason this part supports an LVDS interface

Charles Tsai said:

A 105MHz external clock must be applied at the SCK pin to achieve 5Msps throughput.

Thus - should this not prove "fatal" - to the use of (any) TM4C device noted here?

Poster's requirement: "I need 5 msps or more ADC" - followed by: "Is it possible to connect external ADC with TM4C1294 LPad?" seems (badly) matched.    Of course one can "connect" to a proper ADC Eval board - it is the "Data Transfer Rate" - rather than the "connection" - which is "more properly sought."    (such level of - and attention to: "detail" IS very much required - for such project's success...)

Perhaps the need for "5 msps" deserves (some) justification - in light of the (few) facts - thus far - arriving.