I'm having a really strange issue which I have been debugging for over a week now, so I thought I would see if anyone here had any ideas. I will explain the relevant parts of my system then explain what I am seeing.
I am using DMA along with CAN together to receive CAN messages. In this setup, all of the hardware mailboxes are dedicated to an individual CAN message except for the last one. The last one is set to trigger DMA to transfer the received message into a buffer which is periodically processed. This DMA channel has another DMA channel in its chain register. This secondary channel writes and indicator of what index in the CAN message buffer was written last.
We have an external real time clock which feeds a 32kHz tick into the NHET module. We use the HTU in order to retrieve the time current time.
This system has been tested and working for a long time, but we have one piece of code which has issues when any message gets into the last CAN mailbox and should be transmitted with DMA. When it receives one of these messages, the message is not transmitted, the time is never retrieved, and the memory browser in the debugger shows BAD0BAD0 for all values when refreshed until the code execution is paused.
This is the code we use to get the time. After receiving a CAN message and DMA starts processing it, it gets stuck at the while loop.
htuREG2->GC = htuREG2->GC & 0xfffeffff; // Disable transfer unit while((htuREG2->BUSY0) & 0x01000000); SubSecTimestamp t = RTCBuffer; htuREG2->GC = htuREG2->GC | 0x00010000; // re-enable the transfer unit
In addition to this, the CAN message never shows up in the destination buffer. From what I can tell from the DMA registers, it thinks the CAN message has been transferred to the buffer and it is waiting on the chained channel to complete. There are no other DMA channels active, and it should only copy one byte, so it shouldn't take any time.
This behaviour happens when interrupts are enabled or disabled, so I don't think some interrupt is causing issues when the CAN message is received.
The thing that is very strange about this to me is that DMA and the HTU seem to both be effected, even though I don't know any way they are linked.
Here are register states for DMA before and after sending the CAN message.
521177 13 R Dma_GlbCtrl 0x0000000B 0x00010300 R Dma_ChnPnd 0x0000000B 0x00000000 R Dma_Stat 0x0000000B 0x00000000 R Dma_HWChnEnaSet 0x0000000B 0x00000024 R Dma_HWChnEnaRst 0x0000000B 0x00000024 R Dma_SWChnEnaSet 0x0000000B 0x00000000 R Dma_SWChnEnaRst 0x0000000B 0x00000000 R Dma_ChnPrioSet 0x0000000B 0x00000024 R Dma_ChnPrioRst 0x0000000B 0x00000024 R Dma_GlbChnIntEnaSet 0x0000000B 0x00000000 R Dma_GlbChnIntEnaRst 0x0000000B 0x00000000 R Dma_ReqAssg0 0x0000000B 0x00010203 R Dma_ReqAssg1 0x0000000B 0x04150607 R Dma_ReqAssg2 0x0000000B 0x08090A0B R Dma_ReqAssg3 0x0000000B 0x0C0D0E0F R Dma_ReqAssg4 0x0000000B 0x10111213 R Dma_ReqAssg5 0x0000000B 0x14151617 R Dma_ReqAssg6 0x0000000B 0x18191A1B R Dma_ReqAssg7 0x0000000B 0x1C1D1E1F R Dma_PrtAssg0 0x0000000B 0x00400400 R Dma_PrtAssg1 0x0000000B 0x00000000 R Dma_PrtAssg2 0x0000000B 0x00000000 R Dma_PrtAssg3 0x0000000B 0x00000000 R Dma_FTCMap 0x0000000B 0x00000000 R Dma_LFSMap 0x0000000B 0x00000000 R Dma_HBCMap 0x0000000B 0x00000000 R Dma_BTCMap 0x0000000B 0x00000000 R Dma_BERMap 0x0000000B 0x00000000 R Dma_FTCIntEnaSet 0x0000000B 0x00000000 R Dma_FTCIntEnaRst 0x0000000B 0x00000000 R Dma_LFSIntEnaSet 0x0000000B 0x00000000 R Dma_LFSIntEnaRst 0x0000000B 0x00000000 R Dma_HBCIntEnaSet 0x0000000B 0x00000000 R Dma_HBCIntEnaRst 0x0000000B 0x00000000 R Dma_BTCIntEnaSet 0x0000000B 0x00000000 R Dma_BTCIntEnaRst 0x0000000B 0x00000000 R Dma_GlbIntFlg 0x0000000B 0x00000000 R Dma_FTCIntFlg 0x0000000B 0x00000000 R Dma_LFSIntFlg 0x0000000B 0x00000000 R Dma_HBCIntFlg 0x0000000B 0x00000000 R Dma_BTCIntFlg 0x0000000B 0x00000000 R Dma_BERIntFlg 0x0000000B 0x00000000 R Dma_FTCAOffst 0x0000000B 0x00000000 R Dma_LFSAOffst 0x0000000B 0x00000000 R Dma_HBCAOffst 0x0000000B 0x00000000 R Dma_BTCAOffst 0x0000000B 0x00000000 R Dma_BERAOffst 0x0000000B 0x00000000 R Dma_FTCBOffst 0x0000000B 0x00000000 R Dma_LSFBOffst 0x0000000B 0x00000000 R Dma_HBCBOffst 0x0000000B 0x00000000 R Dma_BTCBOffst 0x0000000B 0x00000000 R Dma_BERBOffst 0x0000000B 0x00000000 R Dma_PrtCtrl 0x0000000B 0x00000000 R Dma_RamTstCtrl 0x0000000B 0x00000000 R Dma_DbgCtrl 0x0000000B 0x00000000 R Dma_WpReg 0x0000000B 0x00000000 R Dma_WpMsk 0x0000000B 0x00000000 R Dma_PrtAChnSrcAddr 0x0000000B 0x00000000 R Dma_PrtAChnDstAddr 0x0000000B 0x00000000 R Dma_PrtAChnTrCnt 0x0000000B 0x00000000 R Dma_PrtBChnSrcAddr 0x0000000B 0x00000000 R Dma_PrtBChnDestAddr 0x0000000B 0x00000000 R Dma_PrtBChnTrCnt 0x0000000B 0x00000000 R Dma_ParCtrl 0x0000000B 0x00000005 R Dma_ParErrAddr 0x0000000B 0x00000000 R Dma_MpCtrl 0x0000000B 0x00000000 R Dma_MpStat 0x0000000B 0x00000000 R Dma_Pr0Strt 0x0000000B 0x00000000 R Dma_Pr0End 0x0000000B 0x00000000 R Dma_Pr1Strt 0x0000000B 0x00000000 R Dma_Pr1End 0x0000000B 0x00000000 R Dma_Pr2Strt 0x0000000B 0x00000000 R Dma_Pr2End 0x0000000B 0x00000000 R Dma_Pr3Strt 0x0000000B 0x00000000 R Dma_Pr3End 0x0000000B 0x00000000 DMA CH 2 ISADDR: 08015F1C DMA CH 2 IDADDR: 08019038 DMA CH 2 ITCOUNT: 00420001 DMA CH 2 CHCTRL: 0000A01F DMA CH 2 EIOFF: 00040004 DMA CH 2 FIOFF: 00000020 DMA CH 2 CSADDR: 00000000 DMA CH 2 CDADDR: 00000000 DMA CH 2 CTCOUNT: 00000000 DMA CH 5 ISADDR: FFF7E140 DMA CH 5 IDADDR: 08015F04 DMA CH 5 ITCOUNT: 00420003 DMA CH 5 CHCTRL: 0003F01F DMA CH 5 EIOFF: 00080008 DMA CH 5 FIOFF: 00200000 DMA CH 5 CSADDR: 00000000 DMA CH 5 CDADDR: 00000000 DMA CH 5 CTCOUNT: 00000000
521177 13 R Dma_GlbCtrl 0x0000000B 0x00014300 R Dma_ChnPnd 0x0000000B 0x00000004 R Dma_Stat 0x0000000B 0x00000004 R Dma_HWChnEnaSet 0x0000000B 0x00000024 R Dma_HWChnEnaRst 0x0000000B 0x00000024 R Dma_SWChnEnaSet 0x0000000B 0x00000000 R Dma_SWChnEnaRst 0x0000000B 0x00000000 R Dma_ChnPrioSet 0x0000000B 0x00000024 R Dma_ChnPrioRst 0x0000000B 0x00000024 R Dma_GlbChnIntEnaSet 0x0000000B 0x00000000 R Dma_GlbChnIntEnaRst 0x0000000B 0x00000000 R Dma_ReqAssg0 0x0000000B 0x00010203 R Dma_ReqAssg1 0x0000000B 0x04150607 R Dma_ReqAssg2 0x0000000B 0x08090A0B R Dma_ReqAssg3 0x0000000B 0x0C0D0E0F R Dma_ReqAssg4 0x0000000B 0x10111213 R Dma_ReqAssg5 0x0000000B 0x14151617 R Dma_ReqAssg6 0x0000000B 0x18191A1B R Dma_ReqAssg7 0x0000000B 0x1C1D1E1F R Dma_PrtAssg0 0x0000000B 0x00400400 R Dma_PrtAssg1 0x0000000B 0x00000000 R Dma_PrtAssg2 0x0000000B 0x00000000 R Dma_PrtAssg3 0x0000000B 0x00000000 R Dma_FTCMap 0x0000000B 0x00000000 R Dma_LFSMap 0x0000000B 0x00000000 R Dma_HBCMap 0x0000000B 0x00000000 R Dma_BTCMap 0x0000000B 0x00000000 R Dma_BERMap 0x0000000B 0x00000000 R Dma_FTCIntEnaSet 0x0000000B 0x00000000 R Dma_FTCIntEnaRst 0x0000000B 0x00000000 R Dma_LFSIntEnaSet 0x0000000B 0x00000000 R Dma_LFSIntEnaRst 0x0000000B 0x00000000 R Dma_HBCIntEnaSet 0x0000000B 0x00000000 R Dma_HBCIntEnaRst 0x0000000B 0x00000000 R Dma_BTCIntEnaSet 0x0000000B 0x00000000 R Dma_BTCIntEnaRst 0x0000000B 0x00000000 R Dma_GlbIntFlg 0x0000000B 0x00000020 R Dma_FTCIntFlg 0x0000000B 0x00000020 R Dma_LFSIntFlg 0x0000000B 0x00000000 R Dma_HBCIntFlg 0x0000000B 0x00000000 R Dma_BTCIntFlg 0x0000000B 0x00000000 R Dma_BERIntFlg 0x0000000B 0x00000000 R Dma_FTCAOffst 0x0000000B 0x00000000 R Dma_LFSAOffst 0x0000000B 0x00000000 R Dma_HBCAOffst 0x0000000B 0x00000000 R Dma_BTCAOffst 0x0000000B 0x00000000 R Dma_BERAOffst 0x0000000B 0x00000000 R Dma_FTCBOffst 0x0000000B 0x00000000 R Dma_LSFBOffst 0x0000000B 0x00000000 R Dma_HBCBOffst 0x0000000B 0x00000000 R Dma_BTCBOffst 0x0000000B 0x00000000 R Dma_BERBOffst 0x0000000B 0x00000000 R Dma_PrtCtrl 0x0000000B 0x01000000 R Dma_RamTstCtrl 0x0000000B 0x00000000 R Dma_DbgCtrl 0x0000000B 0x00000000 R Dma_WpReg 0x0000000B 0x00000000 R Dma_WpMsk 0x0000000B 0x00000000 R Dma_PrtAChnSrcAddr 0x0000000B 0x00000000 R Dma_PrtAChnDstAddr 0x0000000B 0x00000000 R Dma_PrtAChnTrCnt 0x0000000B 0x00000000 R Dma_PrtBChnSrcAddr 0x0000000B 0x08015F20 R Dma_PrtBChnDestAddr 0x0000000B 0x08019038 R Dma_PrtBChnTrCnt 0x0000000B 0x00420000 R Dma_ParCtrl 0x0000000B 0x00000005 R Dma_ParErrAddr 0x0000000B 0x00000000 R Dma_MpCtrl 0x0000000B 0x00000000 R Dma_MpStat 0x0000000B 0x00000000 R Dma_Pr0Strt 0x0000000B 0x00000000 R Dma_Pr0End 0x0000000B 0x00000000 R Dma_Pr1Strt 0x0000000B 0x00000000 R Dma_Pr1End 0x0000000B 0x00000000 R Dma_Pr2Strt 0x0000000B 0x00000000 R Dma_Pr2End 0x0000000B 0x00000000 R Dma_Pr3Strt 0x0000000B 0x00000000 R Dma_Pr3End 0x0000000B 0x00000000 DMA CH 2 ISADDR: 08015F1C DMA CH 2 IDADDR: 08019038 DMA CH 2 ITCOUNT: 00420001 DMA CH 2 CHCTRL: 0000A01F DMA CH 2 EIOFF: 00040004 DMA CH 2 FIOFF: 00000020 DMA CH 2 CSADDR: 00000000 DMA CH 2 CDADDR: 00000000 DMA CH 2 CTCOUNT: 00000000 DMA CH 5 ISADDR: FFF7E140 DMA CH 5 IDADDR: 08015F04 DMA CH 5 ITCOUNT: 00420003 DMA CH 5 CHCTRL: 0003F01F DMA CH 5 EIOFF: 00080008 DMA CH 5 FIOFF: 00200000 DMA CH 5 CSADDR: FFF7E140 DMA CH 5 CDADDR: 08015F24 DMA CH 5 CTCOUNT: 00410003
The nhet and htu registers both look the same before and after the crash while waiting in the while loop I mentioned above.
521177 13 R Nhet2_GlbCtrl 0x0000000B 0x00030001 R Nhet2_Pfr 0x0000000B 0x00000701 R Nhet2_Addr 0x0000000B 0x00000000 R Nhet2_Offst1 0x0000000B 0x00000000 R Nhet2_Offst2 0x0000000B 0x00000000 R Nhet2_IntEnaSet 0x0000000B 0x00000000 R Nhet2_IntEnaClr 0x0000000B 0x00000000 R Nhet2_Exc1 0x0000000B 0x00000000 R Nhet2_Exc2 0x0000000B 0x00000000 R Nhet2_IntPrio 0x0000000B 0xFFFFFFFF R Nhet2_IntFlg 0x0000000B 0x0001FFD4 R Nhet2_HrSh 0x0000000B 0x0000000F R Nhet2_Xor 0x0000000B 0x00000000 R Nhet2_ReqEnaSet 0x0000000B 0x00000001 R Nhet2_ReqEnaClr 0x0000000B 0x00000001 R Nhet2_ReqDst 0x0000000B 0x00000000 R Nhet2_Dir 0x0000000B 0x00000000 R Nhet2_DIn 0x0000000B 0x0000AA80 R Nhet2_DOut 0x0000000B 0x00000000 R Nhet2_DSet 0x0000000B 0x00000000 R Nhet2_DClr 0x0000000B 0x00000000 R Nhet2_PDr 0x0000000B 0x00000000 R Nhet2_PDis 0x0000000B 0x00000000 R Nhet2_PSel 0x0000000B 0x00000000 R Nhet2_ParCtrl 0x0000000B 0x00000005 R Nhet2_ParAddr 0x0000000B 0x00000000 R Nhet2_ParPinReg 0x0000000B 0x00000000 R Nhet2_SfPrld 0x0000000B 0x00000000 R Nhet2_SfEna 0x0000000B 0x00000000 R Nhet2_LbPairSel 0x0000000B 0x00000000 R Nhet2_LbPairDir 0x0000000B 0x00050000 R Nhet2_PinDis 0x0000000B 0x00000000 R Nhet2_HWAGCR0 0x0000000B 0x00000000 R Nhet2_HWAGCR1 0x0000000B 0x00000000 R Nhet2_HWAGCR2 0x0000000B 0x00000000 R Nhet2_HWAENASET 0x0000000B 0x00000000 R Nhet2_HWAENACLR 0x0000000B 0x00000000 R Nhet2_HWALVLSET 0x0000000B 0x00000000 R Nhet2_HWALVLCLR 0x0000000B 0x00000000 R Nhet2_HWAFLG 0x0000000B 0x00000000 R Nhet2_HWAOFF0 0x0000000B 0x00000000 R Nhet2_HWAOFF1 0x0000000B 0x00000000 R Nhet2_HWAACNT 0x0000000B 0x00000000 R Nhet2_HWAPCNT1 0x0000000B 0x00000000 R Nhet2_HWAPCNT 0x0000000B 0x00000000 R Nhet2_HWASTWD 0x0000000B 0x00000000 R Nhet2_HWATHNB 0x0000000B 0x00000000 R Nhet2_HWATHVL 0x0000000B 0x00000000 R Nhet2_HWAFIL 0x0000000B 0x00000000 R Nhet2_HWAFIL2 0x0000000B 0x00000000 R Nhet2_HWAANGI 0x0000000B 0x00000000 R Htu2_GlbCtrl 0x0000000B 0x00000000 R Htu2_CPEna 0x0000000B 0x00000001 R Htu2_Busy0 0x0000000B 0x01000000 R Htu2_Busy1 0x0000000B 0x00000000 R Htu2_Busy2 0x0000000B 0x00000000 R Htu2_Busy3 0x0000000B 0x00000000 R Htu2_ACp 0x0000000B 0x00000000 R Htu2_RLBECtrl 0x0000000B 0x00000000 R Htu2_BFIntSet 0x0000000B 0x00000000 R Htu2_BFIntClr 0x0000000B 0x00000000 R Htu2_IntMap 0x0000000B 0x00000000 R Htu2_IntOffst0 0x0000000B 0x00000000 R Htu2_IntOffst1 0x0000000B 0x00000000 R Htu2_BIm 0x0000000B 0x00000000 R Htu2_RLostFlg 0x0000000B 0x00000000 R Htu2_BFIntFlg 0x0000000B 0x00000001 R Htu2_BerIntFlg 0x0000000B 0x00000000 R Htu2_Mp1Strt 0x0000000B 0x00000000 R Htu2_Mp1End 0x0000000B 0x00000000 R Htu2_DbgCtrl 0x0000000B 0x00000000 R Htu2_WpReg 0x0000000B 0x00000000 R Htu2_WpMsk 0x0000000B 0x00000000 R Htu2_Id 0x0000000B 0x00070304 R Htu2_ParCtrl 0x0000000B 0x00000005 R Htu2_ParAddr 0x0000000B 0x00000003 R Htu2_MpCtrlStat 0x0000000B 0x00000000 R Htu2_Mp0Strt 0x0000000B 0x00000000 R Htu2_Mp0End 0x0000000B 0x00000000
Thanks in advance. Let me know if any other information is helpful.
