TMS570LS1224: Issue with the PLL configuration

Hello Bharat,

If BPOS[1:0} (Bypass) is disabled:

• automatic response to the PLL slip is prevented
• ESM/exception is NOT generated
• reset on slip is not generated regardless of the state of the ROS bit
• status bits are set on a PLL slip independent of BPOS[1:0]

If ByPass is enabled:

• PLL slip causes the clock source into GCM clock source 1 to shift from the PLL to the oscillator
• ESM/exception is generated
• reset on slip is generated if ROS is set

So both fields (ROS and BPOS) should be set at the same time. 

Hello Wang,

Thanks for the Information.

From the Dataset , ByPass must to be enabled for ROS to be enabled. That is reason in Halcogen, when i enable RESET on PLL SLIP in Halcogen the other option BYPASS on PLL SLIP is also enabled.

Now i understood why halcogen was doing that.
Thanks for the quick help.

Regards,
Bharat