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TMS570LC4357: TMS570LC TRM documentation errors and clarifications in L2RAMW

Part Number: TMS570LC4357

Hi,

While reading the "TMS570LC43x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual" (SPNU563, May 2014), I found the following errors:

1) Register RAMUERRADDR is mentioned at 3 places in chapter 8 "Level 2 RAM (L2RAMW) Module", but it does not exist.

2) In the same chapter, RAMERRSTATUS[DWDE]'s description talks about single-bit errors, but it should obviously be double-bit errors.

Now, there is something not clear in the L2RAMW documentation:

3) Does RAMCTRL[ECC DETECT EN]=5h disables both ECC errors detection and ECC codes generation? If not, is there a way to disable ECC codes generation? My objective is to write a bad ECC code in RAM in order to test the SECDED mechanism.

Thanks.

  • Hello Etienne,

    Thank you for the feedback on the TRM errors. I will forward them to our documentation staff so that they can be addressed. Note also that there is a link in the document for document feedback that can also be used for you to provide this feedback directly to them. Either way is OK for me.

    In regard to the 3rd point. You are correct in that the ECC generation is not disabled so you can't simply turn off ECC then create a mismatch. There is an alternative method to allow you to write to the ECC memory and create the corruption in this way. This takes some effort in that you have to understand the impact of the ECC code that is written (i.e., single bit or double bit error type).
  • Hi,

    You are talking about enabling RAMCTRL[ECC WR EN] and writing directly to the ECC memory?

    Also, relative to your answer, could you also forward point #3 to the documentation team in the sense that it is not written anywhere that RAMCTRL[ECC DETECT EN] does not disable ECC code generation. In other words, it is not written anywhere that ECC code generation cannot be disabled.

    Thanks.
  • Hello Etienne,

    Yes, I am suggesting writing directly to the ECC memory.

    I will forward the content improvement to add the information that ECC generation still happens even if ECC is disabled.