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TMS570LC4357: Documentation Details for Hercules Chip Register configurations

Ronaldo Castillo
Prodigy 10 points

Part Number: TMS570LC4357

Does any one know where I can find bit level details of register configuration for TMS570LC4357? For example if you look at  "Table 6-16. Clock Domain Descriptions" of its reference manual (spns195c.pdf), there is no further information on bit setting/options/configurations for any of the registers shown. It only identifies the range of bits for a configuration but does not show the different bit settings for different states.

  • 0
    TI__Guru**** 199516 points

    Hello Ronaldo,

    The column 2 of the table 6-16 shows the bit field and register to disable the clock domain, and the column 4 shows the bit field and register to select the clock source for this clock domain.

    1. The register CDDIS is used to enable and disable the clock domain.

        For example, writing 0x8000 to CDDIS to disable the VCLKA4

    2. GHVSRC, RCLKSRC, VCLKASRC are used to define the clock source for GCLK/VCLK/HCLK/VCLK2, RTI Clock, and the peripheral async clock.

        For example, writing 0x100 to RCLKSRC, RTI module will use OSCIN as its clock source, and divider is (1+1).

        If the OSCIN=16MHz, the RTI clock will be 16/2=8MHz