TMS570LS3137: Output pin indication of internal watchdog trip

Hi Scott,

nRST and nERROR are really two very different pins.

nRST is specifically designed to relay information regarding the reset status of the device and it is asserted when the device goes into reset and is de-asserted when it is out of reset. This will happen irrespective of the source of the reset. It is also a bidirectional pin. This means that it can also be used to create a warm reset on the device through an external pin. i.e., if an external device is connected to the nRST pin, it can assert the nRST pin and cause the device to go through a warm/soft reset. During a warm/soft reset, some of the registers in the device are maintained and the CPU most of the peripherals are reset. It is basically starting over from the reset vector but allows the opportunity for preservation of error registers, RAM content, etc. in order to check for the cause of a prior reset (uncorrectable memory errors, CPU faults, WD faults, etc). The nRST reset method is often prescribed for fault recovery or for use to enter into a safe state.

nERROR is a pin we use to notify the system of an issue within the confines of the MCU. i.e., this tells the system something critical has gone wrong and the system needs to take some action. In some cases as with our companion PMIC TPS65381A-Q1, the nERROR can be monitored and upon surpassing a count threshold, it can assert nRST or nPORRST dependent on the system needs. As you noted, one of the errors in the ESM groups within the the ESM module, is the RTI_WWD_NMI which as part of the ESM Group2 errors would cause an NMI and assertion of the nERROR pin. Note that this is a configurable behavior since the DWWD is programmable to either generate the NMI and nERROR action or to directly cause an nRST event. 

If the DWWD is configured to generate the reset event after a DWWD violation, the associated code should check the SYSESR register as part of the boot up code/reset code to determine the source of the reset and then take appropriate action according to the system needs. Methods for clearing the reset status bits in SYSESR and in the ESM status registers are given in the associated TRM chapters. I believe these bits are write cleared.

On a bit of a side note, if your application is a functional safety application, please make sure you consider the common cause failure mechanisms if you are choosing to use the on chip watch dog functionality. Specifically, consider the implications of clock failures (either frequency drift, jitter, or complete failure) since the same clocks are ultimately used to drive both CPU and RTI functionality. For this reason, many customers choose to use an external WD that is clocked independently of the MCU. 

Also, consider looking at the companion PMIC TPS65381A-Q1 device since it provides the necessary voltage rails for Hercules as well as complimentary nERROR monitoring, Q&A sequence aware WD, and potentially other safety features that would be beneficial to your application Logic BIST, Analog BIST, over temp monitoring, over/under voltage monitoring, over current monitoring, etc).

Hi Scott,

Scott Asher said:

1. The datasheet and technical reference manual mentions that the watchdog module can be configured to generate a system reset for a watchdog violation. In this case, what state would all the I/O pins (GPIO, N2HET, etc.) be in during and after a System reset? Section 4.3 of the datasheet mentions that all I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes high. But I'm not sure, do the I/O pins do the same thing during System Reset and immediately after System Reset as is described for nPORRST in section 4.3? If it does can you point me to where in the documentation is says this?

The same would apply to nRST. I am not certain why we specifically have not mentioned a system reset here as well since both effectively do the same thing with the IO which is to disable the outputs and set as inputs. Note that there is a caveat for output only terminals where it states "All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High. also noted where they will be configured as outputs."

In regard to documentation of this behavior, I agree that this is not explicitly mentioned in the TRM or Datasheet. I will submit a documentation "bug" on this so that we can add it to the list of changes to be incorporated into an up coming release.

Scott Asher said:

2. I also have questions about the N2HET pins that cannot be multiplexed as GIOA or GIOB. The datasheet and technical reference manual mentions that all the N2HET pins can be used as GPIO pins. N2HET section in ref manual mentions using HETDIN command for reading input and HETDSET and HETDCLR for setting/clearing output. If the ones that cannot be multiplexed and GIOA or GIOB are used as GPIO pins instead of N2HET timer functions, can their GPIO logic state (high or low) be set or read from the main routine of the host software running in the TMS570? Or would they still need to be controlled or read from within N2HET Micromachine program loop? Are the HETDIN, HETDSET, and HETDCLR commands available from the main host software routine or can these commands only be used from within the N2HET micromachine program loop?

The NHET pins can easily function as GPIO pins by setting them up and manipulating them as you would any GPIO in a dedicated GPIO module. Simply configure them as input or output and set and clr by either writing directly to the HETDOUT, HETDIN registers or, to be more certain of pin impact, use the HETDSET and HETDCLR registers so that only the bits you choose are impacted. Note that when you read the HETDIN and HETDOUT registers you will also see the states of the pins used for NHET timer functionality so you will need to mask as appropriate to filer unwanted bits. These registers can be accessed directly by the CPU and you don't necessarily have to utilize the HTU or an NHET program to manipulate these pins.