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RM48L530: External watchdog IC to nPORRST or nRST

Niels_D
Prodigy 100 points
Part Number: RM48L530
Other Parts Discussed in Thread: TPS65381A-Q1

Hi,

I am wondering if there is any requirement for an external watchdog connected to an RM48 (or maybe even any CPU in general) when it comes to the type of reset it should assert.
The TPS65381 uses the power-on reset (cold reset), but this IC also does voltage monitoring, so it could be because of that.

The internal watchdog asserts a warm reset, for which also a flag is set during the reset.
The same can be done using the nRST pin of the CPU, which asserts a warm reset as well.
The benefit of this approach is knowing the reason behind the reset, but I am not sure if this is allowed for functional safety.
I could not find any recommendation regarding the type of reset asserted by an external watchdog in the RM48 safety manual nor in the IEC 61508 standard.

Can you help me with this?

Thank you in advance!

  • 0
    TI__Guru 59540 points
    Hello Niels,

    In general, which one you use is a decision that should be evaluated and determined at the system level. You have noted some very good reasons for connecting to nRST and considering that an WD primary concernt and function is to monitor program flow a nRST assertion would definitely serve to correct this type of fault should it occur. Also keep in mind that the nRST can be triggered internally by software directly so it can also be used internally to handle other critical fault types as well.

    With this said, if we consider the use of the Hercules companion device, TPS65381A-Q1, we generally guide our customers to connect it's NRST output to the Hercules nPORRST pin (see application note: www.ti.com/.../spna176a.pdf). This can be explained because of the multi-faceted safety functions that this device performs. i.e., it serves as a Q&A watchdog, nERROR pin monitor, Voltage Supervisor, External enable channel (EN_DRV), over current monitor, etc.) In most of these conditions, asserting the power on reset is necessary to recover from critical faults and/or to hold the device in a reset state as the safe state (with IOs tri-stated) due to a critical fault in either the power supply or internally within the MCU as notified by the nERROR pin.