Team,
A customer of mine is looking for additional information about the EMIF timing. Neither the datasheet nor the TRM are 100% clear. Are there timing diagrams for the following cases?
- Read-Read-Write (access to 16-bit Memory-Device)
- Write-Write-Read (access to 16-bit Memory-Device)
- Read-Read (two 16-bit accesses, resulting from one 32-bit read)
- Write-Write (two 16-bit accesses, resulting from one 32-bit write)
Does the TA time apply in all of these cases? It is also unclear how CS behaves during a 32-bit access, which is split into two 16-bit accesses.
My customer needs these details as they are interfacing the EMIF to a FPGA.
Thanks,
Robert
