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Compiler/TMS570LC4357: R5F-MPU

user5145576
Prodigy 90 points
Part Number: TMS570LC4357

Tool/software: TI C/C++ Compiler

what the difference among memory type of normal, device and strongly ordered?

and shareable and non shareable?

  • 0
    TI__Mastermind 32565 points
    Hi,

    Strongly ordered and device type memories are sensitive to the number of reads or writes performed. A read or write to these memories may cause some effects and hence the CPU does not alter the size or order of the accesses to these memories. These memories are not cached. For this reason the peripheral register memory space is recommended to be configured as device type.
    The SRAM memories can be configured as normal. The accesses to these memory location does not cause any side effects. Also, it insensitive of the order of accesses. These memories can be cached.
    When you configure a memory region as non-shareable, it can be accessed only by the CPU. A shareable memory is shared with other bus masters like DMA or EMAC. Shareable memories cannot be cached on L1 cache. (This device do not support L2 cache)
    For more information on these attributes, please refer to the ARM Cortex™-R5 Technical Reference Manual or ARM® Architecture
    Reference Manual

    Thanks and Regards,
    Veena