RM57L843: rm57l843

Hello Raheel,

I am not aware of the techniques you have mentioned. I am forwarding to a colleague with a little more experience using the EMIF than I. Hopefully he will be able to assist you and provide some guidance.

Hi Chuck

Please update Asap.

Regards;

Hi 

The issue had been reported in the last week. Its been many days and I have no replay. I don't expect TI support to be taking so much time.

Could you please refer to someone who is more technical.

Regards;

Hello Bari,

RM57 has 3 chip selects for async memory, and each one can support up to 64 MB memory.

If the memory device is 16-bit, the EMIF_BA1 is used to provide the least-significant bit A[0], and EMIF_BA0 can serve as the upper address line EMIF_A[22]. To interface 64MB memory (maximum for each chip select), you need another 2 GIO pins for upper address EMIF_A[23] and EMIF_A[24].

If you use GIO pins as the memory address, you need to toggle those GIOs manually to select 4 memory banks:

GIO1--EMIG_A[24] GIO0--EMIF_A[3] Bank
0 0 0 1st 16 MB
0 1 1 2nd 16 MB
1 0 2 3rd 16 MB
1 1 3 4th 16 MB

Hi Wang

Thanks for helping me out. 

If EMIF_BA1 is used as a A[0], EMIFA0 is used as A[1] and so on............., and the last bit EMIF_BA0 is used as a A[22] then it means EMIFA21_RTPCLK will be unused and not connected. WIll you please confirm this?

Regards;

Hi Wang

How is everything.

Please update me.

Regards;

The EMIF_A) will serve as EMIF Addr[22]:

EMIF_BA1 ---- A[0] of Memory chip
EMIF_ADDR[0] ---- A[1] of Memory chip
EMIF_ADDR[1] ---- A[2] of Memory chip
... ...
EMIF_ADDR[21] ---- A[22] of Memory chip
EMIF_BA0 ---- A[23] of memory chip

Thanks Wang

Do you think there could be any other parameter interms of timing signals in selection of flash which is to look for.


Regards;

Wang

Just finalizing the design, I found a mistake and like to reconfirm this. For a 16-bit memory device of 64MB we need 25 address lines not 26 lines. Therefore, we require only 1 address line to access the address. And following will be the connections of our design.



EMIF_BA1 ---- A[0] of Memory chip
EMIF_ADDR[0] ---- A[1] of Memory chip
EMIF_ADDR[1] ---- A[2] of Memory chip
... ...
EMIF_ADDR[21] ---- A[22] of Memory chip
EMIF_BA0 ---- A[23] of memory chip
EMIF_GIO0 ---- A[24] of memory chip

Would you please confirm the upper address lines are correct? I look forward for a quick reply.

Regards;

Wang

Please update,

Regardsl

Hi

I'm waiting for the replay of my previous post. Please also tell me about the following.



1)- The datasheet of RM57L843 says the number of eight-bit GIO Ports are only two with 16 interrupts and having 161 GPIO in total. While the doc spnu562 considers the possibility of 08 ports of eight bit with 32 interrupts possible. It means that all the 145 pins are only available on the pin basis when not used in their original functionality or they can be used on the port basis.



2)- The datasheet says that it provides three CS of Async interface providing 16MB on each of the three CS on EMIF, while the document spnu562 does specify the provision of external memory with GPIO without mentioning any size. When I asked for the support, I have been told that 64MB is possible (as the address range also confirm this). I'm confused with the page 90 of datasheet where it claims to have 64MB frame size and 16MB of actual size. What is the difference between the frame and actual size? and is it possible to use the 64MB 16-bit device?

Regards;



Regards;