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RTOS/TMS570LS3137: Questions/Clarification for Errata PBIST#4

Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Tool/software: TI-RTOS

Hello,

I need help in understanding errata_PBIST_4() function.

it will be a great help if  someone clarify below points for me

1. As per  Errata Document SPNZ195g PBIST software needs to rerun the erata function till the test passed but in the latest Halcogen code i dint see test being repeated when test fails.

2. I see Halcogen code is using 1000 PMU counts , i want to understand how its determined to use 1000 Cycles ?

and why do we divide the count by 2? 

pmuCount = pmuCount - pmuCalibration;

PBIST_wait_done_loop = (((INT16)pmuCount/2) - 1000);//sint

3. Test is consider as fail when PBIST time is too short (<80%) or too long (120%) , so then why do we check against <=20 and >=200 in Halcogen code for test failure ?

if ((PBIST_wait_done_loop <= 20) || (PBIST_wait_done_loop >= 200) )

Thanks

Manzoor

  • Hello Manzoor,

    Can you confirm which silicon revision you are using? If you are using the latest version (Rev. D) you will not need to worry about this as it has been fixed. If you are using the older revision, rev.C, mitigation is still needed. For the answers to the specific questions you have asked, I will need to check with one of our engineers that was involved with the debug and implementation of the workaround.
  • Hi Chuck,

    Yes we are still using Rev C , for which i wanted to implement this errata but needed more clarity on the above points.

    Thanks
    Manzoor
  • Not an issue, but I would highly encourage you to evaluate a move to Rev.D if you are not yet in production as many issues such as this are resolved there.

    I am awaiting response from our expert on this topic and will get back to you as soon as I have more information.
  • The workaround implemented in HALCoGen is different from the one presented in the workaround section of the errata document. (Workaround section is included for others who may not have read it recently.)

    The PBIST controller is a memory test state machine that executes a microcode stored in a special PBIST ROM. In earlier versions of the silicon (check the errata document for the silicon version you are using to see if this erratum applies) the sense timing circuit for reading the PBIST ROM might power up oscillating. Each attempt to read the PBIST ROM disrupts the oscillation, and when the timing is correct the read attempt will stop the oscillation. Once the oscillations stop, there are no problems until the circuit is powered off and powered on again. If the read does not stop the oscillations, the resulting misread microcode causes the PBIST to halt without setting an error. Hence the very short execution time. This should help you understand the workaround described in SPNS195.

    The algorithm in HALCoGen is different. It is more sophisticated. The HALCoGen code actually loads custom microcode instructions into the PBIST state-machine RAM that does thousands of PBIST ROM reads. Since it is not executing from the PBIST ROM, ROM misreads don't affect the state-machine. With this algorithm, measuring the execution time is probably overkill.

    Now for those of you who want to know how to program the PBIST state-machine, sorry. That is proprietary information and is not disclosed by TI.

  • Thanks Bob for the explanation .

    it was very helpful.

    Thanks
    Manzoor
  • Hi Bob,

    see the thread below,

    e2e.ti.com/.../1450689


    do this algorithm has to be fixed as suggested in the above link?.


    Thanks
    Manzoor
  • That has been fixed since HALCoGen version 4.04.00 released in April 2015. The current version of HALCoGen is 4.07.00.