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TM4C1290NCPDT: I2C timing (About TDH)

Koichi Ie
Intellectual 270 points
Part Number: TM4C1290NCPDT

Hi,


I want to know the minimum value of Data hold time of I2C master,
but in I2C Characteristics of datasheet, only the value of Nom is listed as below.

I4 TDH Data hold time (master) Min - Nom 7 Max - (system clocks)

Could you tell me the minimum value of TDH?

  • 0
    TI__Guru 72500 points
    Notice that the data hold time is given as a number of system clock cycles. The variation from that time will be primarily from the difference in the rise/fall time of the data line compared to the clock line. For a minimum data hold time it would be the number of system clocks specified minus the clock fall time, plus the data fall time. Those times are primarily based on the capacitance of the clock and data lines and the strength of the pull-up resistors in your system.
  • 0
    Guru 117855 points

    Koichi Ie said:
    want to know the minimum value of Data hold time of I2C master

    In many years - and many, many I2C applications - such "Master Data Hold Time" (alone) has (never) proved a concern.

    My firm's (and clients') findings ... you must be mindful of the impact of:

    • the separation between Master & (especially) the "most distant" Slave
    • the quality of "I2C pcb traces" - and/or cabling - between Master & Slave(s)
    • the "specs" of the "poorest performer" upon your I2C bus
    • robust power & (especially) common ground between Master & (all) Slaves

    Note that the "poorest performing device" upon your I2C bus (must) be accommodated!      And will likely present a "Drag upon your Speed Goals."     Your interest in "Data Hold time" must extend (additionally) to that of "each/every (other) I2C device" - present on your I2C bus.    Our group has found that while such "Set-UP & Hold times" are useful - proper "Signal Edges"are of high importance - as well.    Too high pull-up values (especially those provided "free" by the MCU) and excessive bus capacitance (both noted here by vendor) - combine to "round signal edges" reducing I2C signal robustness.

    In summary - "Data Hold Time" is but "one actor" on the "I2C stage" - other performers must be recognized (and guided) - as well...

  • 0 in reply to Bob Crosby
    Intellectual 270 points
    Bob-san,

    Thank you for your relpy.

    I will reply to my customer.
    Depending on customer's request, we will ask you additional questions.

    Best Regards,
    Koichi Ie
  • 0 in reply to cb1_mobile
    Intellectual 270 points
    Hi cb1_mobile,

    Thank you for your relpy.

    So it will be helpful.

    Best Regards,
    Koichi