RM48L952: SPI Delay Register (SPIDELAY) Documentation Inconsistencies

Hello,

In datasheet SPNU503B, in section 24.9.19 SPI Delay Register (SPIDELAY), the values donot match up with the bit fields. 0 - 1FFh refers to a 9 bit field, but the bits are only 8 bits for all of the C2TDELAY, T2CDELAY, T2EDELAY and C2EDELAY. The range should be 0 - FFh, correct?

Thanks